Design Reuse

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Missed IP07 Conference ? Or just want to review what you have heard in a session ?
See IP 07 Presentations from IP Industry Leaders online.

IP07 (December 5-6, 2007) will be the 16th edition of the working conference on hot topics in the design world, focusing for the past 7 years on IP-based electronic system and held in the well known Silicon and Alliance Nanometer Valley in the French Alps.

Celebrating D&R’s 10th anniversary,
"State of the Art in Patent Licensing Support" by Mike McLean, Vice President of IPinsights
Today, many technology companies are looking for licensing opportunities outside their core markets; the semiconductor licensing landscape has expanded to include downstream system-level products; and, a new breed of licensor known as the “non-practicing entity” or “troll” has entered the fray (...)
Acquiring External IPs and internal Reuse practice in large companies: A decade of experience?
"Achieving Maximum Reuse Leverage: Lessons from benchmarking 1000+ IC projects" by Ron Collett, CEO of Numetrics Management Systems, Inc.
Great Expectations probably describes the feeling prevalent throughout the semiconductor industry when reuse first entered the IC design paradigm more than ten years ago. Reuse was supposed to unleash huge boosts in development productivity and output that would offset the Design Productivity Gap. Has it happened? If not, why not?
Which IP Business and what Star IPs for the future?
"Emerging Opportunities for Semiconductor IP" by Jack Browne, Vice President of Marketing of MIPS Technologies
Since the beginning of the semiconductor IP industry in the early 90s, we’ve moved from special purpose functionality to relatively simple processor cores to today’s wide range of very complex superscalar cores that offer multithreading, multicore and other high performance functionality. Now the industry is looking to the next step as customers want new and larger solutions that encompass more of the functionality on the chip.
"Next Chapter in IP: Enabling Innovation" by Gagan Gupta, Senior Director of Product Marketing of ARC International
The next wave of innovation in IP technology will be driven by compute intensive, consumer applications such as video processing. With the explosion in usage of multimedia-enabled devices, SoCs have to support multiple standards, various resolutions, and enable encode and decode. At the same time, SoC designers are challenged to differentiate their chips from competition in order to command the highest ASP possible.
"The future of IP industry. Are CPUs the only Stars in IP?" Moderated by Richard Wallace, Editor-in-Chief of EE Times
With the participation of MIPS, ARC, ARM and Silicon Hive
A decade of IP Market Analysis and IP activity all around the globe
"The Semiconductor IP Market: Past, Present and Future" by Jim Tully, Vice President, Chief of Research Semiconductors Gartner
Semiconductor IP as a real market can be traced back about 10 years. Over this time the market has changed a lot and a different set of issues now face the industry. Some have said that there is no money to be made in IP yet this sector has outgrown both the EDA and semiconductor markets and is on track to continue that trend. This session will outline the reasons for change in IP and will explore the changing nature of this sector over the next several years.
"IP website as a catalyst of IP industry" by Gabričle Saucier, CEO of Design And Reuse
What to do and what no to do. Trends and Lessons learnt from a decade of experience.
A Visionary forum
Is organized during both days and will give the floor to outstanding speakers for analyzing the past decade and the coming one on all the hottest topics in the IP arena.
  • "A Decade in Library IP and Mixed Analog IPs"
  • Bob Tait, Marketing Director - Consumer Silicon
    Silicon & Software Systems (S3)
    With the participation of ARM, Dolphin Integration, MIPS Technologies, Synopsys

  • "Implementing Security of On-Chip Resources"
  • Jim Lipman, Vice President of Client Services
    Cain Communications
    With the participation of ARC International, Sidense, Certicom

  • "Open Source for Hardware Design"
  • Francois Kleitz, Silicon and IP providers Technical Manager
    Alcatel Lucent
    With the participation of Gaisler Research, Sun Microsystems, Synopsys

  • "Semiconductor IP – Who should be the Standards Torch Bearer?"
  • Warren Savage, CEO
    With the participation of Mentor Graphics, Improv Systems, OCP-IP, The SPIRIT Consortium

  • "What’s needed to service the power conscious emerging mobile video marketplace?"
  • William Billowitch, Marketing Director, IP & EDA Alliances
    Cadence Design Systems
    With the participation of ARC International, MIPS/ChipIdea, Silicon Hive
  • "Collaborative platform for Electronic Subsystem"
  • Bill Martin, General Manager, Intellectual Property Division
    Mentor Graphics Corporation
    With the participation of STMicroelectronics, Palmchip, eSilicon, Mentor Graphics

  • "Highest Quality IP: Dream or Reality?"
  • Dr. Wolfram Büttner, Managing Director, Founder and CTO
    OneSpin Solutions
    With the participation of Cadence, Certess, ST Microelectronics, Infineon, OneSpin Solutions

  • "IP/SoC Prototyping"
  • Huy-Nam Nguyen, Head of System Modelling and Verification Service
    Bull / METASymbiose
    With the participation of EVE, TI, Synplicity, STMicroelectronics

  • "Is networking the solution for interconnect design closure?"
  • Dr. Srinivasan Murali, Research Scientist
    Ecole Polytechnique Federale de Lausanne
    With the participation of Silistix, ST Microelectronics, Arteris, IHP Microelectronics

  • "A decade in standard based IP and what's the future for the next decade"
  • Joachim Kunkel, VP and General Manager, Synopsys
    Technical Conference
    The conference is organized in 3 tracks.

    IP Best Practice track running the first day and covering hot topics such as IP business model, IP integration, IP security, IP management and delivery.

    A Design track running on both days with 30 presentations focusing on innovating IPs and IP based SoC / Platform designs as well as contributions in advanced design techniques with emphasis on Power optimization, Mixed signal Design.

    A High Level Modeling and Verification track running also on both days with 28 high level contributions with a first half day on high level modeling (TLM, System C) followed by contributions on formal verification and architectural synthesis.

    Exhibitor track and Open Forum. In the exhibitor track exhibitors will have a chance to present their companies and their latest products. It will be followed by an Open Forum of 25 short presentations with strong industrial practices such as verification, IP design methodology, IP generator, test and simulation.
    IP O7 Best Prizes
    CEA_leti This year due to D&R 10th anniversary and extensive press presence special, highlight will be given at the Award Ceremony hold the second day under the sponsorship of CEA/LETI and the LSI IP Design Award Committee in Japan.

    The Conference is proud to recognize the excellent, novel, innovative and highly practical design ideas that authors contribute.
    Excellence in design – whether it be within an IP block or a complete system continue to be the future of the IP based electronic system industry.
    Sponsored by
    MIPS Technologies
    OneSpin Solutions
    Mentor Graphics


    Espace Congres du World Trade Center
    5 place Robert Schuman
    38 000 Grenoble

    IP/SoC Conference Archives

    The foils of previous year's "IP Based SoC Design" events presentations are available online: