Design Reuse

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Exhibition Program Committee Best IP Awards 2007
Exhibitor track [2] (Dec. 6, 8:15-10:45)
  • "Ultra-Low Power? Think Multi-ASIP SoC!" by Gert Goossens from Target Compiler Technologies

  • "EVE" by Luc Burgun

  • "Accelerating Product Development with IP Subsystems" by Rick Tomihiro from Mentor Graphics

  • "What's missing? An efficient intranet IP Reuse infrastructure" by Gabriele Saucier from Design And Reuse

  • "ASIC Prototyping with FPGAs" by Mike Dini from The Dini Group

  • "A Formal Verification Process to Ensure Error-free IP" by Michael Siegel from OneSpin Solutions

  • "Breaking the 10G Barrier" by Tony Pialis from Snowbush/Gennum

  • "Ansoft" by Rémy Fernandes