Design Reuse
Search


EETimes
Home Conference Program Exhibition Advisory Board Registration Practical Information D&R Seminar


Panel: IP vision for FPGA : Do complex FPGA designs rely on the use of vendor-created and third-party IPs ?
Wednesday, December 3, 2008, 2:30 PM - 4:00 PM | Room: Auditorium

Do Complex FPGA design rely on the use of vendor-created and third-party IPs ?

Vendor IPs

* Is the IP FPGA offer satisfying the market demand?
* Does netlist encryption constitute an obstacle to FPGA IP delivery
* Business model of vendor provided IPs
* How to improve knowledge dissemination ,licensing and distribution

Third Party IPs

* How does the vendor select Third IP partners
* Are Third party IP programs of better proven quality ?
* How is their non obsolescence guaranteed?
* How can the end user know promptly on reasonably usable existing IP
* What about the dependency versus software tools

Chairperson:
   

Dick Selwood
Embedded Technology Journal
Dick has been involved with FPGAs since he helped launch Actel in Europe many years ago. Since then he has watched their development from glue logic to entire SoC replacements with interest and wonder. He is currently Europe Editor for Techfocus Media, publishers of FPGA and structured ASIC Journal, after many years in PR and marketing communications.


Panelists:
   

Francois Kleitz
Silicon and IP Providers Technical Manager
Alcatel Lucent

   

Stuart Nisbet
Director of IP Development
Xilinx
Stuart Nisbet has been at Xilinx for over 12 years and currently holds the position of IP Director. His new role includes managing a diverse IP portfolio, from Wired to Wireless, through to more horizontal based IP.
Stuart also plays a part in guiding the IP division with respect to Verification and Quality initiatives.
He holds an MENG from Edinburgh University

   

Mark Dickinson
Vice President of Altera's European Technology Cente
Altera
Mark Dickinson joined Altera in 1998 as technical director of the European Technology Center, building the group to the centre of expertise in system and DSP design that it is today. An ETC group was tasked with creating Altera s Excalibur embedded processor solutions. In 2000, Dickinson’s responsibilities were expanded to include all aspects of the company s embedded processor strategy and he was appointed vice president. More recently, Dickinson has been driving the company’s strategy in system-level design, in particular developing system-level solutions for a number of the company’s key market segments. Dickinson holds a degree in physics from Oxford University and a PhD in electronics from Birmingham University. His previous experience includes electronic system and semiconductor design and management positions at test equipment manufacturers and communications companies.

   

Tom Moore
Director, IP Development
Actel
Tom Moore is Director of IP Engineering and Advanced Solutions in Actel Corporation. He has over 20 years experience in the industry and a particular interest in re-usable IP and the tools and deployment models to enable it. In Actel he manages IP Engineering and pioneered the use of SPIRIT, the development of IP Deployment tools and the introduction and optimization of ARM processors into Actel s portfolio. Prior to joining Actel 4 years ago, he was CEO of Silaria Limited which produced advanced scalable and configurable microprocessors for the networking market. He is based in Dublin, Ireland and leads teams in Ireland and at Actel s Silicon Valley headquarters.

   

Ralph Morgan
VP of Engineering for Digital IP
Synopsys
Ralph Morgan is currently VP of Engineering at Synopsys, Inc. where he manages development of Digital IP, Verification IP, and advanced Datapath IP for the Synopsys DesignWare portfolio. He has a strong interest in IP Quality and standards that help designers to efficiently and reliably integrate IP into complex SoC designs. Mr. Morgan received his Masters of Science in Electrical Engineering in 1986 from the University of Washington and since then has held a variety of positions in ASIC Design and EDA. He has been a member of the Synopsys DesignWare IP development team for the last 13 years.

   

Gabriele Saucier
CEO
Design And Reuse
Gabriele Saucier received her PhD from the University of Grenoble, where she was a professor and headed a research lab on Integrated System Design. She has published more than 350 papers in the design and EDA fields. Dr. Saucier is an IEEE fellow for her contributions in synthesis, test generation and fault tolerance. Leaving her university career, in the 1990s she founded a synthesis company, IST (Innovative Synthesis Technologies), mainly dedicated to FPGA synthesis, and in 1997 Design and Reuse, dedicated to IP-based design. She has launched two successful conferences – Euroasic and IP/SoC.