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Panel: SOC Configurability -- Balancing Manufacturing and R/D Costs
Thursday, December 4, 2008, 11:00 AM - 12:00 AM | Room: Auditorium

The increasing complexity of SoCs brings escalating design costs to semiconductor vendors. These costs are reaching a level where dedicated SoCs can no longer be designed for any and every application. They must instead be designed to be more flexible. In this way the high design costs can be amortized over several different end applications. Chips that can be used in multiple applications need a high degree of post-manufacturing configurability. This is likely to be achieved through various combinations of software programing, embedded non volatile memory, FPGA (including embedded FPGA) architectures, and several other means.

Developing an optimum architecture for these emerging SoCs is one of the biggest challenges facing the entire semiconductor industry. The economic basis of future chip design rests on this. Get it right and the industry goes from strength to strength. Get it wrong and the industry risks stagnation.

  • What is the optimum configuration architecture for next generation SoC? Are particular architectures appropriate for particular situations?
  • How will the industry respond to the need for soft IP/content? What are the service revenue opportunities of satisfying this content during the lifetime of devices in the field?
  • What are the design challenges presented by these flexible devices?
  • Who will be the winners and losers in this emerging industry environment?

    Chairperson:
       

    Jim Tully
    Gartner
    Jim Tully is vice president and chief of research for semiconductors at Gartner Dataquest. He joined the company 17 years ago and researches topics across the semiconductor spectrum. Particular areas of focus include emerging technologies, intellectual property, design services and long-term industry trends. Before joining Gartner, Tully worked with Racal Electronics, initially as a system architect and engineering manager focusing on computer networking. He later moved into worldwide marketing management and business management. Before this, he held design roles within the Armstrong Organization (now Mitsubishi), Ferranti, Rediffusion Cable TV and the UK Atomic Energy Authority. In these roles he designed and specified a wide range of electronic systems including computers, communications systems, consumer products and industrial measurement equipment. Dr. Tully holds Master of Science and PhD degrees in electrical and electronic engineering, and an MBA.


    Panelists:
       

    Ian Phillips
    ARM
    Graduating from University of Swansea in Wales in 1975, Ian Phillips spent the next 23 years in various electronic companies and roles in the UK, before joining ARM in Cambridge in 1998. As Principle Staff Engineer he reports into the the Board and is responsible for making sure that emerging Science and Technology are aligned to Strategic Business needs; a role which takes him into the Research and Business community across Europe where he is quite well know. Complementary to this he supports various advisory and steering roles in UK and EU Government, as well as for University Research Programmes.

       

    Philippe Magarshack
    STMicroelectronics
    Philippe Magarshack is Group Vice-President of Technology R&D and General Manager of Central CAD and Design Solutions at STMicroelectronics.

    After graduating from Ecole Polytechnique and Ecole Nationale Supérieure des Télécommunications, Philippe joined AT&T Bell Labs in the US, where he participated in the design of their 32-bit microprocessor family from 1985 to 1989. In 1989 he joined Thomson-CSF in Grenoble, France, and took responsibility for libraries and ASIC design kits for the military market.

    In 1994, he joined the Central R&D Group of SGS-THOMSON (now STMicroelectronics), where he held several roles in CAD and Libraries management for advanced CMOS and BICMOS processes. Since 2005, he now heads ST’s Central Library and CAD organization, which defines and provides solutions to all ST designers in technologies from 0.35um to 32nm and beyond.

       

    Yakov Levy
    MIPS Technologies
    Yakov Levy Yakov Levy has 25 years of experience in the semiconductor and silicon intellectual property (SIP) industries. Prior to joining MIPS Technologies in August 2006, Mr. Levy held various positions with Adimos Inc., Transmeta Corporation and National Semiconductor, including roles in product marketing, marketing, and VLSI design for processors, peripherals and wireless semiconductors.

    Mr. Levy holds a B.Sc. degree in Electrical Engineering from Ben-Gurion University in Israel.

       

    Dan Hillman
    Transmeta
    Dan Hillman's diverse background spans a range of technology companies and disciplines in chip design, EDA and IP. He began his career at RCA Corporation and Zilog Corporation as a chip designer. Dan spent 11 years at Apple Computer as a hardware manager involved in many projects, he was directly involved in the design of the Apple IIGS, and also led a team that developed the IEEE 1394 (FireWire) Serial Bus. He directly managed Design Compiler development and worked as a Corporate Application Group Director and at Synopsys for eight years. Dan served as vice president of engineering for inSilicon, a provider of communications semiconductor intellectual property. Dan served as Vice President of Engineering for Virtual Silicon Technology, a privately held supplier of semiconductor intellectual property. And most recently, Dan is Vice President of Engineering at Transmeta Corporation.

       

    Syed Zahid AHMED
    Menta/Lirmm
    Syed Zahid AHMED is Technical Director at Menta and a Doctoral candidate researcher at LIRMM. At Menta he also serves as chief scientist and is responsible to direct the company towards the latest technological advances and future trends in industry and academics to innovate eFPGA architecture and product strategies. At LIRMM his research includes Heterogeneous MPSoC and NoC to investigate merging of advantages of MPSoC , NoC and FPGAs to create new reconfigurable paradigms to help industry solve several of its challenges especially power consumption. Prior to joining Menta he spent almost one year in Fraunhofer Institute ESK (Munich) and LIRMM for research related with FPGAs and NoC. He holds BSEE with honours from U.E.T. Taxila, PAKISTAN in 2002, MSEE from TU-Darmstadt GERMANY in 2006. He has more then four years of multinational research & industrial experience. His favorite research areas include Chip design, Reconfigurable architectures, FPGA architecture design & prototyping, MPSoC, NoC embedded systems and analysis of global technological trends in microelectronics.