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Seminar: Network on Chip
Thursday, December 4, 2008, 1:00 PM - 2:30 PM | Room: 2


Srinivasan Murali
Co-founder and CTO


Olivier Bringman

Combination of Design-Time and Run-Time Routing for Adaptive NoC Architectures under Timing Constraints


In this presentation, new routing strategies that combine design-time and run-time techniques by use of static timing predictability to satisfy timing constraints and dynamic techniques to cope with failed Network-on-Chip components. This can be done by applying global communication analysis with integrated fault simulation, which includes timing budgets for satisfying given timing constraints. Therefore new application analysis techniques are applied to take advantage of the knowledge of the application as well as the NoC interconnection structure in order to provide analysis results in adequate time. The result of communication analysis can be used to derive potentially conflicting packet transfers via the on-chip network architecture and provides refined timing budgets to guide the dynamic packet-routing algorithms. The dynamic packet-routing algorithm are able to dynamically adapt the routing in case of malfunctioning network resources with respect to pre-calculated timing budgets.


Antonio-Marcello Coppolla
ST microelectronics
Nowadays, SOC for the embedded consumer market, are customized to the consumer application. They are based on multiple processing elements on the same die. Due to the application complexity and usage in final products, SOCs are evolving toward a set of heterogeneous cores with special set of instructions to speed up the application coupled with hardware accelerators that are running at a lower speed, offering the right level of performance, flexibility and size. In this presentation we will introduce the concept of interconnect processing unit (IPU) and we illustrate the unique features and how IPU could be used to connects all processing elements in a SoC


Srinivasan Murali
Co-founder and CTO

In recent years, the number of processor/memory and hardware IP cores on a Systems on Chip (SoC) is rapidly increasing. Today s SoCs comprise several tens of blocks and in the near future, there will be hundreds of blocks on the chip. In many application domains, such as multi-media processing, wireless and tele-communication, the bandwidth requirements between the cores in the SoC is also rapidly increasing. The SoC performance will be increasingly determined by the ability of the communication infrastructure to efficiently connect the different cores. The system architecture design paradigm is already progressively shifting from computation-centric to communication-centric. To tackle the communication complexity, a networks-based interconnection infrastructure, Networks on Chip (NoC), has recently emerged. In this seminar, I will present design methods for building efficient NoC solutions. I will show how NoCs and the design methods can reduce design efforts and help achieving design closure. Moreover, I will show how NoCs help in achieving energy-efficient systems, meeting application performance requirements.


Dr. Srinivasan Murali is a co-founder and CTO of iNoCs. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chip IPs. His interests also include thermal modeling and reliability of multi-core systems. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium, VLSI-SoC) as program committee member/session chair and is a reviewer for many leading conferences and journals. He received a best paper award in the DATE 2005 conference and the EDAA outstanding dissertation award for his work on interconnect architecture design. He has over 30 publications in leading conferences and journals in this field.