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Home Conference Program Exhibition Advisory Board Registration Practical Information D&R Seminar


Session: High Level Modeling (2)
Wednesday, December 3, 2008, 4:30 PM - 5:30 PM | Room: 1

Moderated by:
Laurent Ducousso ,
STMicro

  • "How high-level synthesis can raise the efficiency of design reuse" by Thomas Bollaert from Mentor Graphics Corporation

  • "UML-based Design of a JPEG-LS IP via Axilica FalconML" by Scott Moyers, Robert Thomson, Vassilios Chouliaras & David Mulvaney from Axilica

  • "SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology" by Gaurav Kumar-Verma & Rudra Mukherjee from Mentor Graphics