Design Reuse

Home Conference Program Exhibition Advisory Board Registration Practical Information D&R Seminar

Session: NoC & SoC
Thursday, December 4, 2008, 11:00 AM - 12:00 AM | Room: 1

Moderated by:
Srinivasan Murali ,
Co-founder and CTO

  • "A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip" by Thiago PEREIRA & Cesar ZEFERINO from UNIVALI

  • "A Twenty-four Processors System on Chip FPGA Design" by Zhoukun Wang & Hammami Omar from ENSTA ParisTech

  • "Networks-on-Chip with Reprogrammable Interconnections" by Yuriy Sheynin & Elena Suvorova from Saint-Ptersburg University of Aerospace Instrumentation

  • "A new Buffering Algorithm for data and commands over a high speed interconnect" by Manjunath R & Vikas Jain