Design Reuse
Search


EETimes
Home Conference Program Exhibition Advisory Board Registration Practical Information D&R Seminar


Session: Verification (2)
Thursday, December 4, 2008, 1:00 PM - 2:30 PM | Room: 3

Moderated by:
Thierry Pfirsch
Alcatel Lucent

  • "Generic and Automatic Specman based Verification Environment for Image Signal Processing IPs" by Abhishek Jain, Mahesh Chandra, Arnaud Deleule & Saurin Patel from STMicroelectronics

  • "Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms" by Frank Schirrmeister, Sam Tennant & Markus Willems from Synopsys

  • "Transactions in an OVM SystemVerilog Verification Environment" by Rich Edelman from Mentor Graphics

  • "TRACE BASED APPROACH FOR UNIT LEVEL DEBUG AND VERIFICATION OF C/C++ IP MODELS" by Amit Nene & Swaminathan Ramachandran from Texas Instruments