Design Reuse

Purchase Conference Proceedings

Keynote Talks

Impact of Submicron Technologies  
IP Management and Collaborative Design 

IP/SoC Design 
IP/SoC Design Methodology
  • "IP Modeling and Reuse for SoC Design Using  Standard Bus" by  Imed Moussa and Thierry Roudier, TNI-Valiosys (France)
  • "Tuning Fork - A Tool For Optimizing Parallel Configurable Processors" by Shay Gal-On, Steve Novack, Oz Levia, Improv Systems (USA)
  • "Synthesizable Analog IP" by Navraj Nandra, Barcelona Design Inc. (USA)
  • "ParaGraph - Shrinking the Parameter Space of IP utilizing Parameter Domains" by Vasco Jerinic, Dietmar Mueller, Chemnitz University of Technology (Germany)
  • "IP Design for Dynamically Reconfigurable SoCs" by Tobias Oppold, Wolfgang Rosenstiel, University of Tuebingen  (Germany)
  • "An Integrated Formal Approach for System on Chip" by Kong Woei Susanto, University of Glasgow (UK)

Verification IP IP Business Models Design Forum  IP Interface and Embedded Platform Hardware / Software Integration
  • "Co-simulation and Communication Synthesis for Intellectual Properties IPs Based SOCs: Approach and Experimentation" by M. Marzougui, M. Abid, R. Tourki, Electronic and Micro-Electronic aboratory. Monastir (Tunisia); A. Baganne , LESTER Laboratory. U.B.S (Lorient France)
  • "System-level Exploration of Queuing Management Schemes for Input Queue Packet Switches" by Chen He, University of Texas at Austin (USA); Marcello Lajolo, NEC USA, C&C Research Labs (USA); Margarida Jacome, University of Texas at Austin (USA)
  • "Software Rich Chips" by Paul McLellan, VAST Systems Technology (USA)
  • "Exchange of hardware dependent software IPs" by Patrick Blouet, ST Microelectronics (France); Gabriele Saucier Design And Reuse (France)

Verification and Emulation

Platform Based Design and Embedded System

Development Tools and Platforms
  • "FPGA to ASIC Strategy for Communication SoC Designs" by Rick Mosher, AMI Semiconductors (USA)
  • "An IP-based SOC Design Kit for Rapid Time-to-Market" by Dr Robert Deaves, Dr Andrew Jones, SuperH (UK)
  • "DAvE - Software based system evaluation in the pre-silicon phase" by Timo Bierbaum, Infineon technologies (Germany)
  • "Object-Oriented Synthesis, Modelling and Partioning for SoC Design" by M. Winterholer, C. Schulz-Key, T. Kuhn, W. Rosenstiel, University of Tuebingen ( Germany)
Debugging and Test

  • "Design-for-Test for SoC - Is there a fork in the roadmap?" by Ron Press, Mentor Graphics (USA); Richard Illman, Cadence Design Foundry (UK)
  • "An Embedded Processor Architecture with extensive support for SOC debug" by Richard Curnow, Mark Hill, Andrew Jones, SuperH (UK)
  • "Behavior Analysis for SoC Debugging" by Scott Sandler, Yu-Chin Hsu, George Bakewell, Bassam Tabbara, Novas Software (USA)
  • "Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO" by  Andre Schneider, Karl-Heinz Diener, Günter Elst - Fraunhofer Institute for Integrated Circuits (Germany); Eero Ivask, Jaan Raik, Raimund Ubar - Tallinn Technical University (Estonia)

Far East Activities in IP Exchange and  IP Based SoC Design

  • "IP Exchange Activities and IP Needs for Japanese Electronics Market" by Motoaki Ito, Nobuyuki Miyazaki and Shojiro Mori, IPTC Corporation (Japan)
  • "Activities of SIPAC in IP/SoC industry of Korea" by  Shiho Kim, SIPAC (Korea)
  • "Si-Soft: A national research program for IP/SoC Design Promotion" by  Prof. Chen-Yi Lee, CIC (Taiwan)
Communication and Verification
 Medea (Toolip) Project Overview
  • "Tools and Methods for IP" by Ralf Seepold, FZI (Germany)
  • "Experiences in Formal Checking of a DSP IP Core" by Nguyen H.N., Koumou P., Bull S.A.,METASymbiose S.A. (France); Candaele B., Sarlotte M., Antoine C., Emeriau S., Thales Communications (France)
  • "A next generation interconnect concept to design high performance SoC's" by Carsten Demuth , Infineon (Germany)

Report on the Activities of the VSIA DWG on Virtual Component Quality

  • "A Parallel TCP/IP Offloading Framework for a TCP/IP Offloading Implementation" by Juan M. Solá-Sloan, Isidoro Couvertier, Universidad de Puerto Rico Mayaguez Campus (Puerto Rico)
  •  "Static RTL Analysis of Multi Clock Domain Designs" by Mark Langer, Steffen Rülke,Fraunhofer IIS Erlangen/Branch Lab DA, Dresden (Germany); Alexander Krebs, Frank Dresig,AMD Saxony Limited Liability Company & Co. KG, Dresden Design Center (Germany)