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Seminar: Computational Models for Embedded Software
Thursday December 3, 2009, 10:45 - 12:15 | Room: Mont Blanc

Embedded Systems interact with the physical world where multiple events happen at once and hence reconciling sequential software and the concurrency of the real world with considerations for timeliness, reactivity, robustness, resource management and other non-functional properties represent a key challenge in embedded system design.
This seminar intends to address comparatively the large variety of computation models (eg. dataflow vs. timed systems, KPN, synchronous/reactive systems), Domain Specific Modeling for some application domain (Avionic, SDR, etc.) and to discuss features of real-time operating systems (eCos, Nucleus, LynxOS, etc.).

Chairperson:

   

Huy-Nam Nguyen
Bull S.A.S.


Speakers:

   

Fabrice Lemonnier
Thalès
Summary

Parallelisation is now the only solution to combine high performance and low power. A more important number of multicore exist on the market and facing this volatile market, the industrials have a 3 dimensional problem to choose a multicore for their products : a perennial solution, adequation to there application domains and programmability. This paper proposes an approach which try to solve this 3 problems. The multicore approach is the one elaborated in the Ter@ops project. The adequation to the application domain has been solved by proposing a hardware architecture able to embed the dedicated accelerators which will provide best ratio performance/power consumption. Regarding the programming issue of parallel architectures, we developed a design toolset to parallelise and map the application on the architecture and to optimize the code executed by the accelerator. Concerning the sustainability, we propose FPGA technology which is a stable market. The latest products are now able to embed a multicore architecture.

Bio

Fabrice Lemonnier is a senior Research Engineer at Thales Research and Technology (TRT), Embedded Systems Lab. His main research activities are on multi-processor embedded architectures (FPGA, MPSoC). He is coordinator of Ter@ops project about MPSoC architecture and tools. Before joining TRT, he has worked on software interface standardization for military avionic modules (RTOS and communication) for THALES Airborne Systems. In THALES Optronics, he has worked on methods to improve the algorithm architecture adequation for image processing and on parallel architectures to implement intensive computing algorithms. In 1996, he received the PhD degree from Ecole des Mines de Paris on dedicated architectures for image processing specifically Mathematical Morphology segmentation.

   

Peter Marwedel
Technische Universität Dortmund, Germany
Mapping of Applications to MPSoCs

Abstract:

Recent technological trends have led to the introduction of multi-core processors and multi-processor systems on a chip (MPSoCs). It can be expected that the number of processors on such chips will continue to increase. Power efficiency is frequently the driving force having a strong impact on the architectures being used. As a result, heterogeneous architectures incorporating functional units optimized for specific functions are commonly employed. This technological trend has dramatic consequences on the design technology. New techniques are required, which map sets of applications onto such architectures. This presentation will provide a brief overview over available mapping techniques. Techniques starting from a given task graph as well as techniques starting from sequential code will be covered. The presentation will provide a summary of the first two workshops specialized on the mapping of applications to MPSoCs.

Bio:

Dr. Peter Marwedel received his Ph.D. in Physics from the University of Kiel (Germany) in 1974. He worked at the CS Department of that University from 1974 until 1989. He is a pioneer and co-inventor of behavioural synthesis and worked on the MIMOLA synthesis and code generation tools (a landmark in this area) until 1986. In 1987, he received the Dr. habil. degree (a degree required for tenure track positions in Germany) for this work.
Since 1989 he is a Full Professor and Chair for Embedded Systems at the CS Department of Technische Universität (TU) Dortmund (Germany). He served as the Dean of that Department between 1992 and 1995. The focus of the group led by Dr. Marwedel is on code generation techniques for embedded systems. The efficiency of embedded software, in particular energy efficiency, is a key objective.
In 2003, Dr. Marwedel published a well-known text book on embedded system design. In the same year, he received the teaching award of his University. He is a member of the ARTIST European network of excellence on real-time and embedded systems and an affiliated member of the Hipeac European network of excellence on high performance embedded systems. He contributes to the education of students in the Embedded System Design programs at ALARI, Lugano (Switzerland). Also, he organized an internship program for students of Indian Institutes of Technology at TU Dortmund. For a number of years, he was the representative of the DATE conference at ASP-DAC.
In his work, Dr. Marwedel has bridged the gap between academic research and industrial exploitation. He is also heading (as a CEO) the local technology transfer centre ICD e.V. ICD is in charge of transforming research results into industrial products. ICD has designed several embedded system design tools for industrial customers.

   

Eyal Bergman
Director of Product Marketing
CEVA
Architecture oriented C optimizations

Abstract:

Know your hardware! That’s what it’s all about. Using programming guidelines derived from the processor’s architecture can dramatically improve performance of C applications. In some cases, it can even make the difference between having the application implemented in C and having it implemented in assembly. Well written C code and an advanced compiler that utilizes various architectural features often reach performance results similar to those of hand written assembly code. A quick survey of assembly coding drawbacks should make it fairly clear why real-time programmers need architecture oriented programming guidelines in their toolkit.

Bio:

Eyal Bergman serves as a Director of Product Marketing for CEVA. In his role, he is responsible for all Marketing aspects related to CEVA’s DSP products. Prior to this, Mr. Bergman was the Application Solutions Department Manager at CEVA. Mr. Bergman has worked for CEVA & DSP Group since 2000, and held several development and managerial R&D positions. Mr. Bergman holds MSc & BSc degrees in computer sciences from Bar-Ilan University.