IPESC
Home Conference Program Exhibition Advisory Board Press Group Practical Information


Seminar: The future of Computing: Massively Parallel Computing
Wednesday December 2, 2009, 11:00 - 12:30 | Room: Mont Blanc

Today, anyone can have a single-precision supercomputer in their desktop at an affordable price of less than $2,000 and very soon petaflop clusters of double-precision floating-point designs will be accessible to a large public for less than 1M$

The emphasis of recent years on multi- and many-core architectures has changed and fragmented the landscape of computer architectures, since increasing processor clock rates no longer is a viable way for manufacturers to increase performance. This Massively Parallel Computing seminar will map out architectural trends in parallel computing to include: silicon-level platforms (as illustrated by the TSAR project), massively multiprocessor architectures and wide-area distributed systems. All these platforms have in common that they aggregate a large number of processing elements (in the range 103-105) to offer a huge computing potential. The issues that make it difficult to fully realize this potential are numerous: Minimization of computational overheads of parallel and distributed applications, providing predictable performance at multiple levels of the computing stack, energy efficiency, usability (e.g., programming language support for data-parallel applications), or maintainability (e.g., ability to efficiently identify and repair problems).
The seminar will cover fundamentals of massively multi-core processor architecture, operating system and programming language support for parallel hardware and parallel applications, system support for debugging parallel applications, impact on emerging hardware trends on large-scale data processing system design and will discuss comparatively available alternatives.

In this seminar, we will decrypt and sort out the potentiality hidden behind the numerous messages of product providers.

Chairperson:

   

Nguyen Huy-Nam
Bull S.A.S./METASymbiose S.A.S


Speakers:

   

Prof. Alain Grainer
UPMC/Lip6
Summary

Prof. A.Greiner will present the Catrene research project TSA Rwhich is focused on the design and application of many core processor architectures targeting tera-flops performance. To achieve this objective, TSAR addresses a large range of topics including Cache Coherence protocol design, application specific GALS NoC design and Optimal Compilation for multi-core/multi-thread processor.
TSAR’s originality lies in the fact that it provides specific hardware to handle a Cache Coherence and Memory Consistent Protocol, thus making it different from other projects working on the same topic.

Biography

Alain GREINER has a permanent position as a professor at University Pierre & Marie Curie, after working at BULL from 1985 to 1989 as the project leader for the VLSI design of the Basic Processing Unit of the DPS7000 computer, the most powerful mainframe in this family. He was director of the MASI Laboratory from 1994 to 1997. He was the project leader for the ALLIANCE CAD system, a public domain VLSI CAD system , distributed and used in more than 250 universities worldwide. He is the technical co-ordinator of the SoCLib project. He is presently the head of the SoC department of the LIP6 Laboratory. His research interests include computer and micro-network architecture, CAD tools for VLSI and System on Chip. He has published more than 100 scientific and technical papers, reports and chapters in specialised volumes.

   

Frédéric Pétrot
TIMA
Summary

This talk presents a hardware data migration mecanism that aims to minimize the miss penalty in large scale on-chip multiprocessor. This mecanism is fully transparent to all layers of software, and thus does not require application or OS support.
The research for such a strategy is quite challenging, as it requires to ensure at every instant a correct data addressing, to ensure stability of the system, to avoid the creation of congestion spots and be efficient enough to justify its use.
The first experiements, using a cycle accurate system simulation environment, are quite promising: the average performance gain on scientific applications is around 50%.

Biography

Frédéric Pétrot received the PhD degree in Computer Science from Université Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004.
From 1989 to 1996, F. Pétrot was one of the main contributors of the open source Alliance VLSI CAD system (The Alliance Team got the Seymour Cray award in 1994).
Since 1996, he headed the work on the definition and implementation of the Disydent environment, oriented toward the specification and implementation of multiprocessor SoCs.
He joined TIMA in September 2004, and holds a professer position at the Ensimag, Institut Polytechique de Grenoble, France.
Since 2006, he heads the System Level Synthesis group of TIMA that focuses on CAD, Architecture and Software for MPSoC.