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Seminar: TLM Verification for Systems-on-Chip
Thursday December 3, 2009, 14:30 - 16:00 | Room: Mont Blanc

This seminar discusses a new system verification methodology that is keeping pace with the latest development on designing complex systems at electronic system level (ESL). For ESL design the system description language SystemC has become the de-facto standard and transaction-level modeling (TLM) has become widely accepted to describe the communication and computation parts of a system using well-defined interfaces. TLM-based virtual prototypes are used for many different tasks, e.g. early SW development. As SW development based on TLM-based virtual platforms is possible long before the silicon is available, the design productivity increases significantly. In order to take profit from the increased productivity at electronic system level, the still existing bottleneck of functional verification has to be addressed. Therefore, in recent years different methodologies and approaches have been developed which target the verification of TLM designs and virtual prototypes. In this tutorial, different verification tasks at electronic system level are considered and it will be discussed to what level verification of TLM-models can be done by today's verification methodologies. The seminar introduces TLM+ as a new level of abstraction which is well suited for efficient system verification and presents novel techniques for verifying RTOS properties and assertion-based AMS verification.



Oliver Bringmann



Volkan Esen, Michael Velten, Wolfgang Ecker
Infineon Technologies
TLM+: A New Abstraction for Successful Verification?

Modeling at higher than RTL abstraction levels for early SW development has become substantial within state-of-the-art SoC design processes. So called Virtual Prototypes (VPs) mainly modeled with the de-facto standard language SystemC at the transactional level are being developed. Yet, verification of these VPs has become a challenge as the complexity of the next generation SoC platforms is increasing. Current verification methodologies for transaction level models (TLMs) reflect mainly adaptations of existing RTL verification methodologies. However, the key concept of RTL verification methodologies is the higher abstraction level of the testbench architecture with regard to the Design Under Test (DUT). By applying such architectures to TLMs - especially with newly developed testbenches - the probability of using the same programming structures of the DUT when modeling the verification components increases. This reduces the credibility of the results to a dangerous level. Therefore, it is necessary to develop new abstraction techniques which go beyond the TLM abstraction, in order to ensure that the testbench abstraction is higher than the DUT abstraction, reducing the resemblance in modeling. Within this seminar we introduce new abstraction techniques which we refer to as TLM+. We present examples of how the abstraction level can be raised beyond current TLM and discuss the applicability of the TLM+ methodology for designing verification components.

Volkan Esen is Engineer for System Level Design and Verification at Infineon Technologies. He received his diploma in electrical engineering in 1998 from TU Darmstadt and has a PhD degree from Technical University of Munich where he developed a new description language for temporal assertions covering multiple levels of abstraction. Currently, Volkan Esen focuses on research in the field of ESL-Verification of transaction level platform models.


Marcio Oliveira, Markus Becker, Wolfgang Mueller, Henning Zabel
University of Paderborn/C-LAB
PSL for the Verification of RTOS Properties

Virtual prototyping of Systems-on-Chip and embedded systems has to cope with the hardware platform and the execution of different software tasks scheduled by an operating system. We present an approach for fast RTOS simulation in combination with the application of IEEE P1850 PSL. For this, we first introduce basic concepts of our abstract SystemC RTOS library for fast simulation. Based on the library, we present PSL assertions for the verification of RTOS properties.

Wolfgang Müller received his diploma and doctorial degree from Paderborn University in 1989 and 1997, respectively. He is heading the group of Advanced Design Technologies at C-LAB, a joint R&D institute of Siemens and Paderborn University. Dr. Müller is member of ACM and IEEE Cs and published over 150 articles and several books. Dr. Mueller has over 15 years of experience in Hardware/System description languages and their application. His current interests focus on methodologies, tools, and languages for the verification of Embedded Systems and Systems-on-Chip.


Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
University of Tübingen
Assertion-based Analog Mixed-Signal Verification

The comprehensive consideration of digital and analog parts is the major challenge towards a seamless verification of heterogeneous or mixed-signal systems. For this objective, an assertion-based verification methodology which integrates the novel mixed-signal assertion language and the corresponding automatic checking algorithm is developed. This allows the automatic verification of complex heterogeneous properties that have not yet been automatically verifiable using current approaches. The derived experimental results show the automated integration of the proposed mixed-signal assertions in a simulation environment and give an outline on the broad applicability and the high value of the proposed approach.

Stefan Lämmermann received his diploma degree at electrical engineering at the University of Technology in Darmstadt. He works in the formal methods group as research assistant at the department of computer engineering, head of the department Professor Rosenstiel, at the University of Tübingen. His research interests are assertion based verification methodologies especially for heterogeneous system level verification. He developed the new general mixed-signal-assertion language for online verifying of heterogeneous system.