Design Reuse

EETimes


          Home/Introduction
Program Comittee
Conference Program


DAY 1: December 8, 2004


Room1

Room 2
Session Time
Paper Session
time
Paper

8:00    





















































8:00  







































8:05
8:05

8:10
8:10

8:15 Welcome by Gabriele Saucier
8:15
8:20 8:20
8:25 8:25
8:30 “IP Reuse in the era of sub -90 nm” by  Philippe Magarshack,  Central R&D Group Vice-President, Design Automation, ST Microelectronics
8:30
8:35 8:35
8:40 8:40
8:45 8:45
8:50 8:50
8:55 8:55
9:00 “ Foundries Role in IP Business”  by Rafi Nave, VP of Customer Services, Tower Semiconductor (Israel) 9:00
9:05 9:05
9:10 9:10
9:15 9:15
9:20 9:20
9:25 9:25
9:30 "IP based platform for programmable devices" by Ivo Bolsens, CTO and Vice President, Xilinx (USA)
9:30
9:35 9:35
9:40 9:40
9:45 9:45
9:50 9:50
9:55 9:55
10:00 “Platform ASICs & Serial interconnects - Way of the future” by  Harmel Sangha, Director of Coreware  Marketing & Support LSI Logic,USA
10:00
10:05 10:05
10:10 10:10
10:15 10:15
10:20 10:20
10:25 10:25

10:30 COFFEE BREAK
10:30
10:35 10:35
10:40 10:40
10:45 10:45
10:50 10:50
10:55 10:55




11:00 “IP /SOC Market Overview and Outlook” by Jim Tully (Gartner Dataquest)
11:00
11:05 11:05
11:10 11:10
11:15 11:15
11:20 11:20
11:25 11:25
11:30 “What is or should be D&R’s role in the IP business” by Gabriele Saucier chair of the board D&R

11:30
11:35 11:35
11:40 11:40
11:45 11:45
11:50 11:50
11:55 11:55

12:00 LUNCH

Spirit Press Event
(Room Mont Blanc)
12:00
12:05 12:05
12:10 12:10
12:15 12:15
12:20 12:20
12:25 12:25
12:30 12:30
12:35 12:35
12:40 12:40
12:45 12:45
12:50 12:50
12:55 12:55
13:00 "One Approach to IP Cores: Ten Years and Going Strong" by Hal Barbour from CAST, Inc. (USA)



13:00 "Development of an Arithmetic Operation System of a Variable Digit Number Type" by Hisashi Ito from CASIO COMPUTER CO., LTD. (Japan)

13:05 13:05
13:10 13:10
13:15 13:15
13:20 "IP's Role in Developing the New Consumer Experience" by Cesar Martin-Perez from MIPS Technologies

13:20 "VUPU : Configurable Processor for C Level Design" by Yoshihide Sugiura from Pacific Design Inc. (Japan)
13:25 13:25
13:30 13:30
13:35 13:35

13:40 "IP Business Models: Where is the value in IP?"

Summary
Value is the single most important aspect of IP business transactions. But how do we assess and quantify the value of IP? This interactive panel of IP users and vendors will discuss this important question.

Organized by: Michael Kaskowitz (Mentor Graphics)

Moderated by: Jim Tully (Gartner Dataquest)

Panel Members:
- Jim Venable, Director IP Merger and Acquisitions, Mentor Graphics
- Phil Dworsky, Synopsys
- Philippe Magarshack, STMicroelectronics
- Bart de Loore, Philips
- John Goodenough, ARM
13:40 "A 400µW MPEG-4 Motion Estimation Processor Core for Mobile Video Application" by Junichi Miyakoshi, Yuki Kuroda, Masayuki Miyama & Hideo Hashimoto from Kanazawa University (Japan) & Masahiko Yoshimoto from Kobe University (Japan)
13:45 13:45
13:50 13:50
13:55 13:55
14:00 14:00 "PowerVR MBX - Creating an IP standard for advanced mobile multimedia" by Phil Atkin from Imagination Technologies (UK)

14:05 14:05
14:10 14:10
14:15 14:15
14:20


14:20 "Design of SystemVerilog Assertion IP" by Eduard Cerny from Synopsys, Inc. (USA), Janick Bergeron from Synopsys, Inc. (Canada) & Manoj Kumar Thottasseri from Synopsys, Inc. (India)
14:25 14:25
14:30 14:30
14:35 14:35
14:40 14:40 "The Seven Steps of Formal IP Specification" by Harry Foster from Jasper Design Automation (USA)

14:45 14:45
14:50 14:50
14:55 14:55






15:00 COFFEE BREAK
15:00 "Transaction-Level Modelling and Debug of SoCs" by Bassam Tabbara from Novas Software (USA) & Kamal Hashmi from SpiraTech (UK)
15:05 15:05
15:10 15:10
15:15 15:15
15:20 15:20 "Hierarchical Assertion-based Verification" by H.N. Nguyen from Bull S.A. - METASymbiose S.A.S (France)
15:25 15:25
15:30
"The Platform Based SOC Design that Utilizes Structured ASIC Technology" by Yu-Wen Tsai & Shun-Fu Chuang from Faraday Technology Corp. (Taiwan)
15:30
15:35 15:35
15:40 15:40 "A Verification Environment Creation Infrastructure for Bus-based Systems and Modules" by Jorge Carrillo & Paulo Dutra from Xilinx (USA)
15:45 15:45
15:50 "Platform to Validate System on Chip Design and Validation Methodologies Targeting Advanced CMOS Technologies" by Samuel Picchiottino & Robin Wilson from STMicroelectronics (France)
15:50
15:55 15:55
16:00




16:00


COFFEE BREAK


16:05 16:05
16:10 "Philips Semiconductors Next Generation Architectural IP ReUse Developments for SoC Integration" by Geoff Mole from Philips Semiconductors (UK)
16:10
16:15 16:15
16:20 16:20
16:25 16:25
16:30 "A Comprehensive Approach for Verification of OCP-based SOCs" by Riccardo Mariani & Natale Barsotti from YogiTech SpA (Italy)
16:30 "ESL Standards: Who's doing what and how does it impact IP?"

Summary
The ecosystem of EDA tools, IP, and training and consulting companies is in place for companies to now smoothly transition to ESL design. In this transition, standards for IP development and usage is becoming increasingly important. During this panel discussion, industry experts will focus on discussing the major standards activities for ESL design and will define the role of each in the development and deployment of IP.

Co-Organizers: CoWare, Inc. & Wolfgang Rosenstiel, Univ. of Tuebingen

Moderator: Michael Santarini, EETimes

With the participation of:
- Open SystemC Initiative: Alain Clouard Chairman, OSCI
- SPIRIT Consortium: Ralph von Vignau, Chairman, SPIRIT Consortium
- EDA Vendor Perspective/OCP-IP: Pete Hardee, Product Marketing Director, CoWare, Inc.
- IP Vendor Perspective/OCP-IP: James Colgan, Director, Strategic Alliances, Sonics, Inc.
- IP Vendor Perspective: Joachim Kunkel, VP Engineering Solutions Group, Synopsys
16:35 16:35
16:40 16:40
16:45 16:45
16:50 "SoC IP Qualifcation & Emulation Enviroment" by Mois Navon from Mobileye (Israel)
16:50
16:55 16:55
17:00 17:00
17:05 17:05
17:10 "SOPC Builder, a Novel Design Methodology for IP Integration" by Stefano Zammattio from Altera Corporation (USA)
17:10
17:15 17:15
17:20 17:20
17:25 17:25






17:30 COFFEE BREAK
17:30
17:35 17:35
17:40 17:40
17:45 17:45
17:50 17:50
17:55 17:55








18:00 "The SPIRIT Initiative"

Organizer : Pierre Bricaud (Synopsys) & Ralph von Vignau (Chairman, SPIRIT Consortium)

Moderator: Pierre Bricaud (Synopsys)

With the participation of:
- Ralph von Vignau, SPIRIT chair and Philips
- Serge Hustin, STMicro
- C. Lennard, SPIRIT vice chair and ARM
- Joachim Kunkel, VP IP Engineering Synopsys
- John Wilson, Mentor Graphics
- Ian Mackintosh, VSIA-OCP
- Victor Berman Cadence
18:00 "A Real-Time Video Smoothing IP Implementation using an FPGA-based Environment" by Ridha DJEMAL from LEM (Tunisia), Didier DEMIGNY from ETIS (France) & Rached TOURKI from LEM (Tunisia)
18:05 18:05
18:10 18:10
18:15 18:15
18:20 18:20 "High-Speed Serial fully digital interface between WLAN RF and BB chips" by Michel Eftimakis & Mana Coste from NewLogic (USA)
18:25 18:25
18:30 18:30
18:35 18:35
18:40 18:40 "Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture" by Yusuke Oike, Makoto Ikeda & Kunihiro Asada from University of Tokyo (Japan)
18:45 18:45
18:50
18:50
18:55
18:55
19:00
19:00
"AICP: Aura Intelligent Co-processor for Binary Neural Networks" by Michael Freeman, Michael Weeks & Jim Austin from University of York (UK)

19:05
19:05
19:10
19:10
19:15
19:15
19:20

19:20
19:25

19:25

19:30 BANQUET sponsored by

DAY 2: December 9, 2004

Room1

Room 2
Session Time
Paper Session Time
Paper


8:00
"A Web-Based Environment for the Evaluation and Generation of Complex IP Cores" by Angel Fernández Herrero, Miguel Angel Sánchez Marcos & Marisa LĂłpez Vallejo from Universidad PolitĂ©cnica de Madrid (Spain)  
8:00 "Reusable Verification Environment for Core based Designs" by Teng-Peow Ng, Anjali Vishwanath, Rizal Prasetyokusuma & Ranga Kadambi from Infineon Technologies (AP) Pte Ltd (Singapore)
8:05 8:05
8:10 8:10
8:15 "Challenges in developing a reusable IP core - USB OTG IP case study" by Haridas Vilakathra from Philips (India) 8:15
8:20 8:20 "Debugging SOC Designs with Transactions" by Rich Edelman, Bill Cox & Mark Glasser from Mentor Graphics (USA)
8:25 8:25
8:30 8:30
8:35 "Reducing Time To Market for System On Chip Using Innovative IP Development and Integration Flows" by Sreekanth K.M (India), Lionel Dahyot (France), Rakesh Patnaik (USA) & Vinod Kumar (India) from Texas Instruments 8:35
8:40 8:40 "Is IP Quality Achievable, Measurable and Enforceable through the Design Chain?" by Saverio Fazzarifrom Cadence Design Systems (USA) & Dan Moritz from Virage Logic (USA)
8:45 8:45
8:50 8:50

8:55
8:55



9:00 "NetComposer-II: High-Performance Structured ASIC Programmable NPU Platform for Layer 4-7 Applications" by C.J. Liang from Faraday Technology Corp. (Taiwan, R.O.C.) 9:00
"System Verification Methodology (sVM) applied to Transaction Level SystemC models" by Giles Hall from Verisity
9:05 9:05
9:10 9:10
9:15 "A PowerPC SOC IO Processor for RAID applications" by Gerard Boudon, Thibaud Besson, Veronique Guerre, Pierre Debord & Jacques Rota-Biesdorf from IBM (France)
9:15
9:20 9:20 "What's the State of Verification IP?"

Summary:
The task of verification is increasing exponentially in difficulty and the amount of engineering effort required. Just as designers have been using more, and more complex, silicon IP to rapidly assembly SoCs, they're turning to verification IP to assemble their verification environments and find more bugs, faster.
This expert panel of verification IP providers, designers, and industry analysts will discuss the current state of verification IP. What's working, what's not? Who are the players? How is verification IP being used? What are the latest technologies? What's next?

Organizer : Phil Dworsky, Synopsys

Moderator: Phil Dworsky (Synopsys)

With the participation of:
- Wolfgang Ecker (Infineon)
- Laurent Ducousso (STMicroelectronics)
- Synopsys
- HDL Design House
9:25 9:25
9:30 "STBus Asynchronous Decoupler: an answer to the IP integration issues in future technologies" by Alberto Scandurra & Salvatore Pisasale from STMicroelectronics (Italy) & Daniele Mangano from University of Messina (Italy)
9:30
9:35 9:35
9:40 9:40
9:45 "IP Processor Core Platform Selection According to SoC Architecture: a case study" by Yassine Aoudni & Nader Ben Amor from GMS/LESTER (Tunisia), Guy Gogniat & Jean-Luc Philippe from LESTER (France) & Mohamed Abid from GMS (Tunisia)
9:45
9:50 9:50
9:55 9:55

10:00 COFFEE BREAK 10:00
10:05 10:05
10:10 10:10
10:15 10:15
10:20 10:20
10:25 10:25

10:30 "Platform ASIC: How can Platform ASIC solutions best harness available IP?"

Summary: Platform ASIC solutions have emerged as the new way of generating unique silicon and getting quickly to market with the minimum of cost and risk. Platform ASIC is today's common system-on-silicon (SOC) and to be successful it requires good quality IP. But what IP is available in the various solutions? How can IP vendors sell into this market? What logic fabrics are best suited to next generation IP? Is any IP a pre-requisite to success of Platform ASIC? What IP standards are people really using? Do users care? This interactive panel session will be essential listening for all involved in the ASIC and IP industry, both providers and users. It is intended to explore how IP and Platform ASIC interact today and how these relationships may evolve.

Organizer: Tim Daniels (LSI Logic)

Moderator: Doug Amos, Synplicity, Director European Business Development

with the participation of:
- Alon Kapel, eASIC, GM European Operations
- Tim Daniels, LSI Logic, Technical Product Marketing Manager
- Jean-Luc Couturier, MoreThanIP, Sales Manager, Western Europe
- Arnaud Schleich, PLDA, VP Sales & Marketing
- Bob Beachler, Altera
10:30
10:35 10:35
10:40 10:40
10:45 10:45
10:50
10:50
COFFEE BREAK
10:55 10:55
11:00 11:00
11:05 11:05
11:10 11:10
11:15 11:15 "The Challenge of Keeping IP Usable" by Phil Rose from Cadence Design Systems (UK)
11:20 11:20
11:25 11:25
11:30 11:30 "DesignJet: A Project Management Platform for Collaborative IC Design" by Charles Trappey from National Chiao Tung University (Taiwan), Amy J.C. Trappey, Jiang Liang Hou & Ker Jeng Chang from National Tsing Hua University (Taiwan) & Shiu Yuan Shih from Avectec.com, Inc (Taiwan)
11:35 11:35
11:40 11:40
11:45 11:45 "Solving The IP Selection Problem: Are Quality Metrics Enough?" by Saverio Fazzari & Jean-Michel Fernandez from Cadence Design Systems (USA)
11:50 11:50
11:55 11:55

12:00 LUNCH
12:00 "IP Exchange Procedure: a light formalism to improve communication between IP suppliers and integrators" by Rosamaria Balestri from STMicroelectronics (italy)
12:05 12:05
12:10 12:10
12:15
12:15 LUNCH
12:20 12:20
12:25 12:25
12:30 12:30
12:35 12:35
12:40 12:40
12:45 12:45
12:50 12:50
12:55 12:55
13:00 "Physical Design for Reuse: Strategies and Implementation" by Ralph Escherich & Lane Albanese from ReShape Inc. (USA)
13:00 "Understanding and Extending SystemC User Thread Package to IA-64 Platform." by Joël Vennin from Prosilog, Samy Meftali & Jean-Luc Dekeyser from LIFL - Lille 1 University (France)
13:05 13:05
13:10 13:10
13:15 "Vertical Solution for PCI Express" by Ken Reid from Cadence Design Systems (UK) 13:15
13:20 13:20 "An IP core based approach to the on-chip management of heterogeneous SoCs" by Mark Lippett from Ignios (UK)
13:25 13:25
13:30 "The right IP for your SerDes needs" by Leo Wong from Rambus (USA) 13:30
13:35 13:35
13:40 13:40 "Interface Synthesis in Multiprocessing Systems-On-Chips" by Francesco Regazzoni from University of Lugano (Switzerland) & Marcello Lajolo from NEC USA (USA)
13:45 "A Design of System on a Chip for Voice over Wireless LAN" by Hun-sik Kang, In-ki Hwang, Chan-won Park, Gi-jong Koo & Jae-ho Lee from ETRI (Korea) 13:45
13:50 13:50
13:55 13:55

 
14:00 "Low power microcontroller design techniques for mixed-signal applications" by Ron Landry from AMI Semiconductor (USA)
14:00 "Improving Performance and Efficiency in Embedded Designs Using Multi-threaded and Multi-Core Technologies"

Summary : This panel will discuss the major issues surrounding the continuing problem of how to provide more programmable performance in embedded designs within in the physical and economic constraints of consumer electronic devices. Emerging technologies include multi-threaded embedded cores, multi-core architectures, DSP centric engines and even embedded programmable fabrics. While each approach brings particular benefits to certain SOC applications, many struggle with inherent limitations. This expert panel will discuss the pro's and con's of these different technologies as applied to specific market segments, and put these important design approaches in fair context.

Organizer: Tom Petersen, Director, Product Marketing, MIPS Technologies, Inc.

With the participation of
- Kai-Uwe Killiches, FAE Manager, Europe, LSI Logic
- Sam Fuller, VP, Marketing, AMCC
- Tom Petersen, Director, Product Marketing, MIPS Technologies, Inc.
- Brani Buric, Sr. Director, Product Marketing, Virage Logic
14:05 14:05
14:10 14:10
14:15 14:15
14:20 "Simultaneous Exploration of Power, Physical design, and Architectural Performance Dimensions of SoC Design Space using SEAS" by Nagashyamala (Nagu) R. Dhanwada from IBM Electronic Design Automation (USA) 14:20
14:25 14:25
14:30 14:30
14:35 14:35
14:40 "Die Level Process Monitoring for Mixed Signal Designs" by Bert Vermiere from Ridgetop (USA), Eckardt Bihler from Forturex (Germany) & Doug Goodman from Ridgetop (USA) 14:40
14:45 14:45
14:50 14:50
14:55 14:55

15:00 COFFEE BREAK
15:00
15:05 15:05
15:10 15:10
15:15 15:15
15:20 15:20
15:25 15:25
15:30 "Unleashing the Power of Embedded DRAM" by Peter Gillingham from MOSAID Technologies (Canada)
15:30 COFFEE BREAK
15:35 15:35
15:40 15:40
15:45 15:45
15:50 "Automated Transistor-Level Optimization in Standard-Cell Based Digital Design" by Rob Roy & Debashis Bhattacharya from Zenasis Technologies (USA) 15:50
15:55 15:55
16:00 16:00 "A Design of MAC Hardware Structure for Wireless PAN" by Ji Eun Kim, Young Ae Jeon & Sang Sung Choi from ETRI (South Korea)
16:05 16:05
16:10 "Rapid Protocol Stack development Framework" by Vinaychandra A V S & Girish Dandin from Wipro technologies (India) 16:10
16:15 16:15 "Performances Estimation Metamodel for MDA Based SoC Design" by Mickael Samyn & Samy Meftali from LIFL, Smail Niar from LAMIH-ROI & Jean-Luc Dekeyser from LIFL (France)
16:20 16:20
16:25 16:25
16:30 "Efficient Verification of CAN based System" by Rajesh Thyagarajan & Pitchumani Guruswamy from Wipro Technologies (India)


16:30 "A SystemC based Virtual Prototyping Methodology for Embedded Systems" by Paul Lister, Mike Bassett, Phil Watten, Vincezo Trignano & Ben Jackson from University of Sussex (UK)
16:35 16:35
16:40 16:40
16:45
"Addressing IP Reuse with Formal Verification and Assertion Based Verification" by Andrea Fedeli, Matteo Moriotti & Franco Toto from STMicroelectronics (Italy) 16:45 "Unparalleled Re-Use Driven by Rule-Based Design" by Geoff Steckel from Bluespec Inc.
16:50
16:50
16:55
16:55
17:00
"System Verification Methodology sVM: A Reuse Verification Methodology from Module-level to System-level" by Imed Moussa, Hannes Froehlich & Patrick Oury from verisity Design (France)
17:00
17:05
17:05
17:10

17:10
17:15 "Implementing Verification Components on FPGA" by Rahul Shah from eInfochips Ltd. (India)

17:15
17:20
17:20
17:25
17:25

17:30

17:30

17:35

17:35