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Short Facts about IP/SoC 2004


DAY 1: December 7, 2005


AUDITORIUM
ROOM 1
ROOM 2
Time Panel
Session Time Paper
Session Time Paper
8:00 Welcome by G. Saucier

Keynote Talks Chairman: Paul Miller, Senior Vice President and Group Director, CMP Media Electronics and Software Development Groups







































































































































































































































8:15 "Successful IP Business Models" Doug Pattullo, Technical Director, TSMC Europe BV





























8:45 Tomorrow's Challenges for Today's IP Providers” Keith Clarke, VP of Technical Marketing, ARM (U.K)





























9:15 Selling the Family Jewels: Can IP Flourish in a Fabless Chip Company?” Rob Tobias, Director of IP Marketing, Silicon Image





























9:45 "Branding the Architecture of a Microprocessor" Carl Schlachte, President and CEO, ARC International





























10:15
Coffee Break





























10:45
How Brand enables companies to be more competitive in today’s global SoC industry

Moderated by: Ron Wilson, EETimes
Panelists:
- Carl Schlachte, President & CEO, ARC International
- Tim Messegee, VP Corporate Marketing, Rambus
- Keith Clarke, VP of Technical Marketing, ARM
- Jack Browne, VP of marketing, MIPS Technologies
- Jim Tully, VP Distinguished Analyst, Dataquest
- Chet Silvestri, CEO, MoSys















































































12:05
"SoC/IP Market Overview and Outlook" Jim Tully, VP Distinguished Analyst, Gartner Dataquest 



















12:25
"China's Silicon IP core, the status and future development" Du Jiao, CSIP


















12:45
Lunch


12:45 Lunch

12:45 Lunch























































13:45
The IP challenge in industry
 
Moderated by: Ron Wilson (EETimes) Panelists:
- Douglas Pattulo, Manager Technical Support, TSMC
- Philippe Decamp, Strategic Business Manager, Europe,Denali Software, Inc.
- Harmel Sangha, Director of CoreWare® IP Marketing, LSI Logic
- Kenneth Larsen, Technology Marketing Manager, 0-In verification Business, Mentor Graphics

High Level Modeling
13:45 "IP integration in embedded systems modeling" by Ali Koudri, Samy Meftali & Jean-Luc Dekeyser from LIFL
IP Design

13:45 "FAUST: On-Chip Distributed Architecture for a 4G Baseband Modem SoC" by Yves DURAND, Christian BERNARD & Didier LATTARD from CEA/LETI Best IP Prize Candidate












14:00 "Implementation  of  a  SystemC  Assertion  Library" by Wolfgang Ecker, Volkan Esen, Jacob Smit, Thomas Steininger & Michael Velten from Infineon Technologies





14:05 "Single Poly EEPROM on standard CMOS process" by Frederic BERNARD from SPINTRON Best IP Prize Candidate







14:15 "ESL Requirements for Configurable Processor-based Embedded System Design" by Grant Martin from Tensilica











14:25 "Design and Optimization of Low-Power Processor for Wireless Sensor Network" by zhao gang from VLSI & System Lab, Beijing University of Technology & Wu WuChen from VLSI & System Lab, Beijing University of Technology Best IP Prize Candidate


14:30 "A Novel Modeling and Verification Environment for Rapid IP Prototyping" by Mikhail Baklashov & Manish Bhattarai from Simantix Systems, Inc.














14:45 "A Case Study in Rule-Based Modeling" by Wolfgang Ecker from Infineon Technologies & Volkan Esen from Infineon Technologies & Mieszko Lis from Bluespec Inc. & Thomas Steininger from Infineon Technologies

14:45 "burst count detectable DMAC implementation on AMBA based system" by IN-KI HWANG from ETRI & DO-YOUNG KIM from ETRI Best IP Prize Candidate












15:00 "Cycle Accuracy Analysis and Performance Measurements of a SystemC model" by Smita Ratnam & Aniruddha Baljekar from Philips Semiconductors





15:05 "IP CORE FOR REGULATION VOLTAGE ADJUSTMENT IN ELECTRIC ENERGY DISTRIBUTION SYSTEMS" by Manoel Firmino de Medeiros Jr., Ivan Saraiva Silva, José Alberto Nicolau de Oliveira & Max Chianca Pimentel Filho from UFRN Best IP Prize Candidate







15:15 "Reusing Verilog IP Cores in SystemC Environment by V2SC" by Leila Mahmoudi Ayough, Ali Haj Abutalebi, Ali Iranmanesh & Moji Atarodi from Ascend Design Automation










15:25 "A Low Complexity Register-Exchange Viterbi Decoder for Tail-Biting Convolutional Codes" by suchang chae from ETRI Best IP Prize Candidate
15:30
Coffee Break

15:30 "A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SOC Designs" by Rich Edelman from Mentor Graphics













 

16:45
coffee break
15:45 "A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip" by Paul Heysters, Gerard Rauwerda & Lodewijk Smit from Recore Systems Best IP Prize Candidate










16:00 "Vertical Kits – Are they the real path to Time To Market efficiency?" Tim Barnes, VP of Marketing Europe, Cadence







16:05 "RtrASSoc51-Adaptable Superscalar Reconfigurable Programmable System on Chip – The Reconfigurable tools for DSR a Development System" by Jorge Silva from University of Sao Paulo Best IP Prize Candidate





16:15
Enabling Technologies for Advanced SoC Design:  IPs and vertical kits
 
Moderated by: Tim Daniels, LSI logic
Panelists:
- Daniel Vellou, Leti/CEA
- Gary Delp, LSI logic
- Roddy Urquhart, Synopsys
- Eric Dupont-Nivet, CSO and Co-Founder, Soisic
- Tim Barnes, VP of Marketing Europe, Cadence
- Jim Venable, Mentor Graphics
- Zvi Or-Bach, President and CTO, eASIC

Standards and Business 16:15 "Risk versus Reward: Where Do Your IP Reuse Practices Fall?" by Kathy Werner from Freescale Semiconductor, Inc











16:25 coffee break


16:30 "Market-Driven Open-Cores SoC Experience" by Bohumir Uvacek from Toshiba













16:45 "Integrating a multi-vendor ESL-to-silicon design flow using SPIRIT" by Christopher Lennard from ARM, Mark Noll from Synopsys, Chulho Shin, Chris Baxter & Peter Grun from ARM










Nanotechnology 16:55 "Computational Nano Technology and its impact on Future Electronics" by Chandrasekaran Subramaniam from St. Joseph's College of Engineering, Dinesh.C & Arun Kumar.S.B from MNM Jain Engineering College


17:00 "How to Create Efficient IP Standards and Why You Should Care" by Dan Moritz from VirageLogic & Saverio Fazzari from Cadence













17:15
"IP packaging and delivery based on XML signatures: Best Practice to standard" by Gabriele Saucier, Lassaad Ghanmi & Mourad Hamdoun from Design And Reuse
17:15 "On-chip di/dt Detector IP for Power Supply" by Toru Nakura, Makoto Ikeda & Kunihiro Asada from University of Tokyo Best IP Prize Candidate










17:30 Break
17:30 Break





17:35 "Efficient Power-Saving MAC Processor for IEEE 802.15.3 Wireless Personal Area Networks" by Young Ae Jeon, Ji Eun Kim, Sang Jae Lee & Sang Sung Choi from ETRI





17:45
How reusable is our verification infrastructure?

Moderated by: Sunil Kakkar, Chief Technologist – Verification, Freescale Semiconductor India Ltd
Panelists:
- Janick Bergeron, Synopsys
- Kenneth Larsen, Mentor Graphics
- Michael Lerchenmuller, Cadence
- Simon Johney, Wipro
- Warren Savage, IPextreme
- Mark Hampton, Certess
- Rich Faris, Real Intent, Inc.


17:45 "Business Considerations in SOC IP Procurement" by Kenneth Wagner from PMC-Sierra, Inc. & Alan Nakamoto from PMC-Sierra, Inc.










17:55
Break







18:05 "Integrating 3rd Party IP into Platform ASIC – a Practical Methodology that Ensures Success" by Anand Govind & Ishtiaque Mohammed from LSI Logic Corp.
18:10 "A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach" by david elléouet from IETR/INSA & Nathalie Julien from LESTER/UBS & Dominique Houzet from IETR/INSA

















18:25 "Bridging the Gap between IP Provider and Silicon Design Center" by Ron Landry from AMI Semiconductor
18:25 "Towards Activity Based System Level Power Estimation" by Eike Schmidt from ChipVision Design Systems & Frank Schirrmeister from ChipVision Design Systems

















18:45 "Methodology for protection and Licensing of HDL IP" by Tarun Batra from Cadence Design Systems & Deepak Pant from Cadence Design Systems
18:45
"Development of Low Power MPEG2-Full HD Core" by Masafumi Tanaka from Techno Mathematical Co., Ltd & Yuzo Kuboyama from Techno Mathematical Co., Ltd Best IP Prize Candidate

















19:05 "Automated Implementation Flows based on IP-level constraints and synthesis intent in XML" by Denis Bussaglia from Synopsys & Marino Strik from Philips Semiconductors & Mark Noll from Synopsys & Geoff Moll from Philips Semiconductors & Ralf Gaisbauer from Philips Semiconductors

19:05
"Analog IP Reuse in Nano Technologies" by Sherif Hammouda from Mentor Graphics & Hazem Said from Ain Shams University & Mohamed Dessouky from Mentor Graphics & Mohamed Tawfik from Mentor Graphics & Quang Nguyen from On SemiConductor
















19:25
BANQUET

DAY 2: December 8, 2005


AUDITORIUM
ROOM 1
ROOM 2
Time Panel
Session Time Paper
Session Time Paper
8:15 "SPIRIT Adopters and Testimonials"

Moderated by: P. Bricaud, Synopsys

"Getting the vision implemented : an update on SPIRIT Consortium progress" by Chris Lennard, Vice Chair SPIRIT Consortium

"65 nm SoC/IP Reuse design based on an emerging standard : SPIRIT" by Olivier Florent & Francois Remond, STMicroelectronics Grenoble France

"The SPIRIT standard and SoC Design Efficiency" by Ralph von Vignau , Philips Semiconductor

"Infineon's motivation to join SPIRIT" by Wolfgang ECKER

"LSI Logic’s motivation to join SPIRIT" by Dr Gary Delp

"Freescale’s motivation to join SPIRIT" by Kathy Werner

Specific Modeling 8:15 "Programming Models for SoCs" by Pascal Nsame, Juergen Hilsberg from IBM
SoC Platform Design 8:15 "Design Of Wireless Systems Utilizing Scratchpad Memories" by Goran Panic, Zoran Stamenkovic, Klaus Tittelbach-Helmrich, Jens Lehmann & Gunter Schoof from IHP Microelectronics














8:30 "A Design for Improving the Channel Time Efficiency in Wireless Network" by Ji Eun Kim, Young Ae Jeon, Sangjae Lee & Sang Sung Choi from ETRI


8:35 "A Strategy for Specifying SystemC Micro-controllers Models using the ADL ArchC" by Patricia Freire, Vitor Schwambach & Edna Barros from CIn- UFPE










8:45 "Real-Time video system Design based on the NIOS II processor and uClinux" by Ahmed Ben Atitallah, Patrice Kadionik & Fahmi Ghozzi from ENIS, Patrice Nouel from IXL-ENSEIRB & Nouri Masmoudi from ENIS







8:55 "Large Memory Modeling" by Andjelija Savic from HDL Design House





9:00 "Successful use of an open source processor in a commercial ASIC" by Declan Staunton from Silicon & Software Systems












9:15 "A Multiplier Module Generator Based on Arithmetic Description Language" by Naofumi Homma, Yuuki Watanabe, Kazuya Ishida & Takafumi Aoki from Tohoku University & Tatsuo Higuchi from Tohoku Institute of Technology Best IP Prize Candidate
9:15 "5c Over AV Link: A Comparison of Architectures" by Vinay A. Somanache from Synopsys & B.U. Chandrashekar from Synopsys














9:30 "Challenges in PCI Express IP-Based Implementation" by Sriram Swaminathan from Rambus Chip Technologies (Pvt) Ltd & Prakash Bare from Rambus, Inc


9:35 "Transaction Level Model of IEEE 1394 serial bus link layer controller IP core and its use in the software driver development" by Filip Rak from Evatronix S.A. & Wojciech Sakowski from Silesian University of Technology




















9:55 coffee break

9:55 coffee break
10:00 coffee break




























10:30 Verification IP for IP Verification: Who is leading whom ?

Moderated by: Chris Lennard, ARM
Panelists:
- Joachim Kunkel, VP Engineering, Synopsys
- Kenneth Larsen, Mentor Graphics
- Eric Esteve, PLDApplications
- Aleksandar Randjic, HDL Design house
- Michael Lerchenmuller, Cadence

Verification and Simulation 10:30 "Novel techniques for very high speed instruction set simulation" by Nagendra Gulur from Texas Instruments
Network on Chip 10:30 "A NoC-based communication framework for seamless IP integration in complex systems" by Fabien CLERMIDY, Didier VARREAU & Didier LATTARD from CEA/LETI



















10:50 "High Speed Connected Component Labeling as a Killer Application for Image Recognition Systems by Dynamically Reconfigurable Processor" by Noriyasu Matsuno & Mitsumasa Yoshimura from IPFlex Inc.


10:55 "Efficient creation of peripheral simulation from specifications" by Nagendra Gulur from Texas Instruments & Archana Shetty, Nisha Nair & Shilpa R from University Visvesvaria College of Engineering















11:10 "Hardware/Software Partitioning and Interface Synthesis in Networks On Chip" by Francesco Regazzoni from ALaRI, University of Lugano & Marcello Lajolo from NEC Labs America, Inc.







11:30 "Connecting reality and simulation: Couple high speed FPGAs with your HDL simulation" by Stefan Reichör from Gleichmann Electronics Research & Martina Zeinzinger from Gleichmann Electronics Research & Markus Pfaff from University of applied sciences, Hagenberg










11:30 "Design and FPGA Implementation of a Interpolative Neural Network for Digital Image Zooming" by Sheng - Hsien HSIEH from Department of Electrical Engineering, I-Shou University & Ching-Han CHEN from Department of Electrical Engineering, I-Shou University


















11:50 lunch

11:50 lunch





12:00 Lunch


























































13:00 How to protect IP in the “new world?” and what business models can protect IP the best?

Moderated by: Jim Tully, VP Distinguished Analyst, Gartner Dataquest
Panelists:
- Gary Delp, CTO, VSI Alliance
- Ralph von Vignau Chairman SPIRIT Consortium, CTO, Philips Semiconductors
- Grant Martin, Chief Scientist, Tensilica
- Ken Wagner, Director, PMC Sierra

Industrial Verification and Methodology 13:00 "Unique Approach to Verification of Complex SoC Designs" by Arie Komarnitzky, Nadav Ben-Ezer & Eugene Lyubinsky from Avnet ASIC
Algorithm and Design Methodology 13:00 "Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs" by Mark Lippett from Ignios












13:15 "Verification methodology for standards-based IP & SoC" by Andy Montador from Cadence Design Systems
13:15 "Core based power optimization methodology for Complex ASSPs" by Veena Chakravarthi from Centillium Communications & Gurumurthy K S from UNiversity College of Engineering












13:30 "A Unified DFT Verification Methodology" by Stylianos Diamantidis, Iraklis Diamantidis & Thanasis Oikonomou from Globetech Solutions
13:30 "Generator based Design Support for Reconfigurable System-on-Chip" by Joerg Schneider from TU Dresden & Vincent Kotzsch from Signalion & Rainer G. Spallek from TU Dresden












13:45 "Dynamic Assertion Based Verification using PSL and OVL." by Aniruddha Baljekar from Philips Semiconductors
13:45 "Quantitative Analysis of Fractional Clock Division for Systems-on-FPGA" by Thomas Preusser, Steffen Koehler & Rainer Spallek from TU Dresden












14:00 "New verification methodology for SoC designs" by sudha Raman from STMicroelectronics
14:00 "Wireless Infrared Communication – Simple and Efficient Design Flow" by Frank Deicke from Fraunhofer IPMS & Hagen Graetz from Fraunhofer IPMS












14:15 "Transaction-based Debug of PCI Express Embedded SoC Platforms" by Bindesh Patel from Novas Software & Sean Smith from Denali Software, Inc
14:15 "Design Methodology of UDF and FDF FIR Filtering IP Core for reusable SoC Design" by Umar Farooq, Muhammad Saleem and Habibullah Jamal from UET Taxila










14:30 Coffee Break

14:30 Coffee Break

14:30 Coffee Break

























15:00 Accessing the Value of the Small IP Provider in Today’s Chip Industry

Moderated by: Jim Lipman, Contributing Editor, TechOnLine and SOCcentral
Panelists:
- Nabil Takla, Ceo of Innovative Semi.(IP provider)
- Charles Ng, VP Worldwide Marketing, Kilopass Technology (IP provider)
- George Janac, Founder & Executive Chairman, Giga Scale IC
- Jim Tully, Gartner/Dataquest (semiconductor research analyst)
- Doug Patullo, Technical Director, TSMC Europe BV
- Peter Hirt, Director of IP Partnerships and Procurement, STMicroelectronics

Industrial Design and Methodology 15:00 "IDRT-aware SoC Integration Flow" by Fréderic POULLET, Christophe GAILLARD & Lucille ENGELS from Dolphin Integration
Prototyping and Debug 15:00 "FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions" by KODAVALLA VIJAY KUMAR & NITIN RAVERKAR from WIPRO TECHNOLOGIES

















15:20 "Image Processing Applications On New Generation FPGA’s" by Rahul V. Shah from eInfochips Ltd.
15:20 "FPGAs and Structured ASICs: Low-Risk SoC for the Masses" by Ed Clarke from Altera Corp.

















15:40 "Enabling Rapid Adoption of the AMBA 3 AXI protocol based design with Synopsys DesignWare IP" by Mick Posner from Synopsys
15:40 "FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM" by Rick Mosher from AMI Semiconductor

















16:00 "Designing a CE-ATA Verification Environment for SoC Applications" by Ioannis Mavroidis from Globetech Solutions
16:00 "FPGA Prototyping as a Verification Methodology" by Ron Landry & Ken Pelic from AMI Semiconductor

















16:20 "High Quality IP creation through Efficient Packaging and Multiple Configuration Testing" by Prabuddha Mitra from Synopsys
16:20 "Debug IP for SoC Debug" by William Orme from ARM





16:30













16:40 "The Perils of RF IP" by David Schwan from Micro Linear
16:40 "Time to Find a Bug" by Jens Kjelsbak from IPextreme

























POSTERS
  • "An IP Simulation and Verification Platform Based on FPGA" by DENG wan-ling from South China Univ. of Tech. & ZHENG Xue-ren from South China Univ. of Tech. & FAN Jian-ming from South China Univ. of Tech. & Chen Ling-jing from South China Univ. of Tech. & Chen Guo-hui from South China Univ. of Tech.

  • "Simulation Analysis of Re-engineered Legacy Engine Management System" by Steve Macdonald from Research Scholar & M Kannan from Research Scholar

  • "Aspects of PCI Express Integration in SoC Designs" by Eric Esteve from PLDA & Alain Loge from PLDA & Philippe Legros from PLDA

  • "Mixed Static And Dynamic Memory Modeling Approach for High Density Memories" by Sharan Basappa from HCL Technologies

  • "System Level Design of MPSoC On-Chip Interconnections" by Yuriy Sheynin from Saint-Petersburg University of Aerospace Instrumentation & Ellin Suvorova from Saint-Petersburg University of Aerospace Instrumentation

  • "IP Buisness Model" by Anish Kumar from Dear Born Electronics India Bangalore

  • "Embedded Linux Co-simulation" by Julien Taillard from LIFL & Philippe Marquet from LIFL & Jean-Luc Dekeyser from LIFL

  • "Basic Silicon IP Modules Redesigning at Transistor Level for Efficient ASIC/SOC Development" by Saroj Kumar Satapathy from Tata Elxsi Limited

  • "ALL VIEDO FORMATS TO MPEG2 CONVERTER on a single chip" by SRI HARSHA from WIPRO

  • "CE-ATA: Consumer Electronics Storage Technology Introduction and Hardware Design Challenges" by Mohamed Salem from Mentor Graphics Corporation

  • "From Obsolete Part Replacement To Enhanced Legacy Microprocessor Architectures" by Wojciech Sakowski from Silesian University of Technology & Maciej Pyka from Evatronix S.A.

  • "FIR Approximation of IIR Filter Using Mean Least Square Error in Hilbert Space" by nikzad babaii from ITRC & Ahmad Khademzadeh from ITRC & Shahein Hessabi from Sharif University of Tech. & Abdolreza Nabavi from Tarbiat Modares University













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