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Panel: Portability of Analog IPs in 32nm and beyond?
Tuesday November 30, 2010, 13:30 - 15:00 | Room: Auditorium

Advanced SOC in 32nm and beyond embeds Analog IP in order to interface with external world. While portability of Digital IP is de facto granted, the portability of Analog IP is more and more a challenge. In one end, technical difficulties rise from voltage compatibility and noise environment. In another end, cost of embedding is questionnable as Analog IP are not reputed to shrink very well.

Chairperson:

		Andreia Cathelin Senior Design Expert STMicroelectronics
	Andreia Cathelin (M’04) started her electronic studies at the Polytechnic Institute of Bucarest, Romania and graduated from the Institut Supérieur d’Electronique du Nord (ISEN), Lille, France in 1994. In 1998, she received the Ph. D. degree from IEMN/ISEN, Lille, France regarding the work on a fully-integrated BiCMOS low power – low voltage FM/RDS receiver. From 1997 till 1998, she was with Info Technologies, Gradignan, France, working on analog and RF communications design. Since 1998, she has been with ST Microelectronics, Crolles, France, now in the Technology R&D, Central CAD and Design Solutions, Innovation & External Research design team. She is a senior design expert and her major fields of interest are RF and mmW systems for wireless communications, MEMS devices co-integration and SOI technologies. She is a member of the Technical Program Committee of ISSCC, VLSI Symposium on Circuits and ESSCIRC. She has authored or co-authored more than 80 technical papers and 2 book chapters, and has filed more than 20 patents.

Panelists:

		Pierre Dautriche STMicroelectronics
		Christophe Bernard STEricsson
		Dominique Henoff STMicroelectronics
		Navraj Nandra Synopsys
		Thierry Dumaure Cadence