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Panel: IP and SoC verification what's key to day ? a good verification plan, verification flows, verification services, Verification IPs or all of that?
Tuesday November 30, 2010, 17:15 - 18:45 | Room: Makalu

It is worldwide admitted that verification consumes 80% of the design time and that it is the key issue in Asic and more generally embedded system design.

This panel will focus on a state of the art discussion in terms of challenges and issues and try to answer basic functions:

1. A verification plan and verification objectives have to be established at the beginning of a project and checked through all the design steps. Is this plan easy to establish and to control?

2. The verification tools are proposed by the 3 major EDA vendors , completed by some other vendors offer and operate at various abstraction levels . Is it easy and straightforward to mix match these tools to establish the adequate verification flow .

3. Is it easy to introduce physical verification steps within a verification flow?

4. Due to the complexity of the verification process ,is it convenient to outsource verification tasks to external verification service provider

5. Are Verification IPs an asset to sell tool or verifications services or can they be used independently

6. Is there room left for research in which area What will the future and progresses look like in the Embedded System verification field

Chairperson:

Laurent Ducousso STMicroelectronics

Panelists:

		Huy-Nam Nguyen BULL
		Thomas Goust IP and SOC Verification Team Leader ST Ericsson
	Thomas Goust has started in the industry in 1997, as a formal verification engineer. He is currently verification department manager in ST-Ericsson, responsible of IP, SOC and chipset verification of all 3G and beyond based products.
		Gabriele Zarri Verification IP Solutions Architect Cadence
	Gabriele Zarri is a Verification IP Solutions Architect in charge of requirements definition and deployment for Cadence's OCP and MIPI verification products. He is also currently chairing the Functional Verification Working Group for the OCP-IP organization.