How to optimize Data-flows in a Multicore SoC
Wednesday December 1, 2010, 11:00 - 12:00 | Room: Makalu
The advent of multicore microprocessors is a major breakthrough in the area of processors architecture, as was the adoption of RISC principles twenty years ago. A few years after being adopted by the computer market, multicores now enter widely the Embedded domain, as in the meantime some specific challenges have been successfully addressed by the silicon suppliers in the area of interconnect, partitioning & virtualization, security, debug and power dissipation, At the silicon level, these increased challenges are actually addressed by multiple sophisticated mechanisms distributed in all the internal blocks of the SoC.
Considering more precisely Embedded processors in Networking applications, a whole set of challenging requirements appear when designing a multicore SoC that must sustain high-throughput and low-latency data-flows:
- How can you distribute the incoming packets or frames among the various cores either equally or arbitrarily based on flow classification ?
- How do you efficiently pipeline the various cores and coprocessors for achieving complex protocol stacks and in this case how do all blocks inter-communicate ?
- How do you preserve or restore packet ordering of each single flow at the various processing stages.
- More generally, moving from the simple single-core model where producer/consumer synchronization and atomicity can be resolved thru some very rudimentary mechanism, how do you manage at best the multi-producer, multi-consumer model inherent to the concurrent activity of all the cores and coprocessors working on the same die, ensuring synchronization and atomicity on shared resources ?
In this conference, we will outline the overall architecture of the new QorIQTM P4080 Multicore SoC platform designed by Freescale and optimized for intensive data-flow applications. We will focus on those specific IP blocks called Queue Manager, Frame Manager and Buffer Manager which build the underlying infrastructure to manage all the data-flows between I/O ports, cores and coprocessors, ensuring overall high-throughput and low-latency.
Senior FAE High End processors
|Eric Bost- Dipl. Engineer ESIEE-Paris in Electronics and Computing. Held several positions in customer training, support and pre-sales at leading semiconductor companies in the area of high-end Processors for Computing and Networking. Currently Senior FAE at Freescale Semiconductors with focus on Freescale new QorIQ Multicore processors. |