IP-SOC 2011
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DAY 1: Wednesday December 7, 2011

7:00 - 8:45
Breakfast and Registration

AUDITORIUM
9:00 - 9:25 20th Anniversary Special Talk
Lessons learnt from 15 years of IP web portals :The break Points and the future

By Gabriele Saucier
CEO
D&R




Lessons learnt from 15 years of IP web portals :The break Points and the future

By Gabriele Saucier, CEO, D&R

9:25 - 9:50 20th Anniversary Special Talk
Keynote Talk: Keynote Talk: Semiconductor design IP Market overview: Retrospective and Forecast

By Ganesh Ramamoorthy
Research Director
Gartner Inc




Semiconductor design IP Market overview: Retrospective and Forecast

By Ganesh Ramamoorthy, Research Director, Gartner Inc

9:50 - 10:15 20th Anniversary Special Talk
IP’s 20 year evolution - adaptation or extinction

By Mike Kaskowitz
Infinitedge




IP’s 20 year evolution - adaptation or extinction

By Mike Kaskowitz, Infinitedge

10:15 - 10:45 Break
10:45 - 11:10 20th Anniversary Special Talk
7 Steps for IP Community Synergy: A China Market Based View Point

By Mark Ma
MBA, Founder
Jiatao Industrial




7 Steps for IP Community Synergy: A China Market Based View Point

By Mark Ma, MBA, Founder, Jiatao Industrial

11:10 - 11:35 20th Anniversary Special Talk
Rise and Fall of New Fabless Startups => New Model for IP/ASSP Collaboration

By Marc Miller
Sr. Director of Marketing
Tabula




Rise and Fall of New Fabless Startups => New Model for IP/ASSP Collaboration

By Marc Miller, Sr. Director of Marketing, Tabula

11:35 - 12:00 20th Anniversary Special Talk
The past and the next 20 years? Scalable computing as a key evolution

By Haydn Povey
Director of Marketing, Processor Division
ARM




The past and the next 20 years? Scalable computing as a key evolution

By Haydn Povey, Director of Marketing, Processor Division, ARM

12:00 - 12:25 20th Anniversary Special Talk
A 20/20 look back on 20 years of EDA and IP Innovation

By Phil Dworsky
Director, Strategic Alliances & Publisher
Synopsys




A 20/20 look back on 20 years of EDA and IP Innovation

By Phil Dworsky, Director, Strategic Alliances & Publisher, Synopsys

12:25 - 13:30 Lunch

AUDITORIUM KILIMANDJARO
MONT BLANC
13:30 - 15:00 Panel: FPGAs addressing new markets with the 44 and 28 nm devices

Moderator:
Hal Barbour
President
CAST



Panelists:
- Bob Blake, Product and Corporate Marketing Manager, Altera
- Ron Digiuseppe, Senior Marketing Manager, Intellectual Property Marketing, Xilinx
- Jim Bruister, President, SoC Solutions
- Bill Finch, Senior Vice President, CAST
- Phil Dworsky, Director, Strategic Alliances & Publisher, Synopsys


20th Anniversary Special Talks
Chairman: Mike Kaskowitz(Infinitedge)

15 years of IP management: From Excel spreadsheet to cloud enterprise platform

By Gabriele Saucier
CEO
Design And Reuse




15 years of IP management: From Excel spreadsheet to cloud enterprise platform

By Gabriele Saucier, CEO, Design And Reuse


Interface IP Market Birth, Evolution and Consolidation, from 1995 to 2015. And further?”

By Eric Esteve
IP Nest




Interface IP Market Birth, Evolution and Consolidation, from 1995 to 2015. And further?”

By Eric Esteve, IP Nest


JOHARI Window based business approach for Marketing IP's and IP's based Solutions

By Madhu Parthasarathy
Ittiam Systems




JOHARI Window based business approach for Marketing IP's and IP's based Solutions

By Madhu Parthasarathy, Ittiam Systems


A Real Future for Innovation in Silicon IP Business Models Using Open Source Tools To Drive Higher Customer Value Propositions

By Arthur Low
Crack Semiconductor




A Real Future for Innovation in Silicon IP Business Models Using Open Source Tools To Drive Higher Customer Value Propositions

By Arthur Low, Crack Semiconductor





















13:30 - 14:30
Session: Analog Design
Chairman: Jean-François Pollet (Dolphin Integration)

-"Mixed Signal IP Design Challenges in 28-nm and Beyond" by Dino Toffolon, Paul Hua, Michael Lynch, Brent Beacham, Cameron Lacy (Synopsys Inc.)

-"Is there a “One-Size-Fits-All” SoC PLL" by Jeff Galloway (Silicon Creations)



Break

14:35 - 15:35
Session: IP Design
Chairman: Paolo Pezzati (Cadence)

-"ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification" by Elmar Melcher, Joseana Fechine (DSC-UFCG), Adalberto Texeira, Jorgeluis Guerra, Karina Medeiros (LAD-UFCG)

-"Channel Core Flex: An Advanced Channeliser for Next Generation Digital Radio Receivers" by Dr Steve Parker (RF Engines Limited)

-"Design of a 4 bit accumulator using new 45nm low leaky standard cells" by Dr. Veena Chakravrthi, Prabhavathi P R, Ramya Rajan (BNM Institute of Technology)

15:00 - 15:30 Break Break
15:30 - 17:00 Panel: All roads lead to IP (Commercialization)

Moderator:
Omri Raisman
RosettaIP



Panelists:
- Kurt Shuler , Director of Marketing, Arteris
- Mark Ma, MBA, Founder, Jiatao Industrial
- Gabriele Saucier, CEO, Design And Reuse
- Philippe Quinio , Group Vice President, IP Sourcing & Strategy, STMicroelectronics


Session: Design Methodology
Chairman: Phil Dworsky (Synopsys)

-"Pipeline AES S-box Implementation Starting with Substitution Table" by Valeri Tomashau (LC Engineers, Inc.)

-"A design data management (DM) approach for the SoC era" by Simon Butler (Methodics)

-"Software generated BCH as a way to solve challenges of providing multiple configuration IP" by Michal Jedrak (Evatronix SA), Filip Rak (Warsaw University of Technology), Tomasz Wojciechowski (Evatronix SA)

-"A Digital Design Flow for Differential ECL High Speed Applications" by Oliver Schrape, Milos Krstic (IHP), Gunnar Philipp, Frank Winkler (Humboldt University)

15:35 - 15:50
Break
15:50 - 17:15
Session: Architecture Design I
Chairman: Patrick Blouet (ST-Ericsson )

-"AMBA 4 ACE Coherency for Heterogeneous Multi-Processor SoCs" by Bruce Mathewson, Ashley Stevens (ARM)

-"3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology" by Dominique Houzet (GIPSA-LAB), Mohamad Jabbar (GIPSA-LAB, ENSTA), Omar Hammami (ENSTA PARISTECH)

-"3D Architecture Implementation: a Survey" by Mohamed Jabbar, Dominique Houzet (GIPSA-LAB)

-"Proposal of a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator" by Syuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (The University of Aizu)

-"3D Mania: Powering Smartphone SoCs with Multi-channel TSV DRAMs" by Drew Wingard (Sonics)


17:00 - 17:15 Break

17:15 - 18:45 Panel: Innovation, Patent and Silicon IP business

Moderator:
Gabriele Saucier
CEO
Design & Reuse



Panelists:
- Michael Kaskowitz, Managing Director, Infinitedge
- Marc Miller , Tabula
- Eric Esteve, IP Nest
- Pierre Patrick, CEO, Avenium Consulting
- Omri Raisman , RosettaIP


The Roadmap for IP and System Design Standards

By Shishpal Rawat
Accellera Chair




The Roadmap for IP and System Design Standards

By Shishpal Rawat, Accellera Chair

17:15 - 17:30
Break

17:30 - 18:45
Session: Architecture Design II
Chairman: Olivier Monfort (Dolphin Integration)

-"Co-Designed Cache Coherency Architecture for Embedded Multicore Systems" by Jussara Marandola (University of Sao Paulo), Loic Cudennec (CEA)

-"Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding" by Frederik Naessens, Praveen Raghavan, Liesbet Van der Perre, Antoine Dejonghe (imec)

-" Design of Tezzaron Based 3D-IC for Butterfly NOC Based 64 PE-Multicore" by Omar HAMMAMI, Abir MZAH, Khawla HAMWI (ENSTA PARISTECH)

-"Enabling High Performance SoCs through Multi-Die Re-use" by Andrew Jones, Stuart Ryan (STMicroelectronics)

-"Enabling the design and programming of application-specific multi-processor architectures" by Gert Goossens (Target Compiler Technologies)





19:00 - 21:30 Join the Christmas Party

DAY 2: Thursday December 8, 2011


7:00 - 8:30
Breakfast and Registration

AUDITORIUM
8:45 - 9:15 20th Anniversary Special Talk
Over 20 Years of Embedded Software Development - A Third Way Emerges

By Colin Walls
Mentor




Over 20 Years of Embedded Software Development - A Third Way Emerges

By Colin Walls, Mentor


AUDITORIUM KILIMANDJARO
MONT BLANC
9:15 - 10:30 Panel: Best practice in incorporating innovative design methodologies and new EDA tools in industrial design flows

Moderator:
Juergen Haase
Managing Director
Edacentrum



Panelists:
- Olivier Haller, STMicroelectronics
- Andreas Bruening, ZMDI
- Christian Sebeke, Robert Bosch GmbH
- Gert Goossens, CEO, Target Compiler Technologies


Seminar: Cache Coherence and Verification

Organizer:
Rob Van Blommestein
Jasper





Speaker:
- Paul Martin, ARM
Seminar: Low Power Design Methodologies and Techniques

Organizer:
Huy-Nam Nguyen
BULL





Speaker:
- Georges Lecourtier, HPC Hardware Architect, Bull Servers Development Division
- Floriberto Lima, CEO, SILICONGATE
- Huy-Nam Nguyen, BULL
10:30 - 11:00 Break
11:00 - 12:30 Panel: Coherency Challenges in Next Generation SoCs

Moderator:
Jack Browne
Sonics



Panelists:
- Drew Wingard, Sonics
- Marcello Coppola, STMicroelectronics
- Bruce Mathewson, ARM


Session: Security
Chairman: Huy-Nam Nguyen (Bull)

-"Physical Attacks against Cryptographic Implementations" by Alexandre Berzati (INVIA), Martin Gallezot (INVIA), Alain Pomet (INVIA)

-"Validating Software in Commercial Smart Transmitter for Safety-Critical Applications" by Gopinath Karmakar, Ashutosh Kabra, Jose Joseph, R. K. Patil (Bhabha Atomic Research Centre)

-"Optimized solutions for cryptography and security" by Thierry Pauwels, Sébastien Rabou (Barco Silex)

Session: System Modelling
Chairman: Juergen Haase (Edacentrum)

-"Refactoring Hardware Algorithms to Functional Timed SystemC Models" by Praveen Kondugari (Intel Mobile Communications)

-"Improving SystemVerilog UVM Transaction Recording and Modeling" by Rich Edelman (Mentor Graphics)

-"Application Hardware Modeling: Selective modeling for early prediction of subsystem performances through simulation" by Ming-Hao Kuo, Florian Espalieu, Nathalie Dufayard (Dolphin Integration)

-"Automated Architecture Checking of UML Based SoC Specifications" by Robert Deaves, Samuel Eaton-Rosen (STMicroelectronics)

12:30 - 13:30 Lunch

AUDITORIUM
KILIMANDJARO
MONT BLANC
13:30 - 15:00 Panel: IP Management

Moderator:
Mike Sottak
Wired Island



Panelists:
- Simon Butler, CEO, Methodics
- Andreas Bruening, ZMDI
- Gabriele Saucier, CEO, Design And Reuse
- Ron Digiuseppe, Senior Marketing Manager, Intellectual Property Marketing, Xilinx
- Claire Genevey, Dolphin Integration




Session: Verification
Chairman: Colin Walls (Mentor Graphics)

-"Virtual Platforms and RPB for faster System Verification" by Praveen Kondugari (Intel Mobile Communications)

-"BIG FPGA Boards for ASIC Prototyping" by Mike Dini (Dini Group)

-"Standard Validation Procedures" by Guruprasad Vadhiraj

-"SystemC library supporting OVM compliant verification methodology" by Arkadiusz Koczor (Evatronix SA), Wojciech Sakowski (Silesian University of Technology)

-"Functional Coverage Analysis for IP Cores and an Approach to Scaledown Overall Simulation Time" by mohansrikanth sunkara, Raja jagadeesan (Synopsys India Pvt. Ltd.)






15:00 - 15:15 Join us for Best IP Prize and Lucky Draw




























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