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DAY 1: Tuesday December 4, 2012
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| 8:00 - 9:30 |
Breakfast and Registration
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AUDITORIUM |
| 09:30 - 10:00 |
Keynote Talk: IP Business: Status and Perspectives
 By Gabriele Saucier
CEO
Design And Reuse
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| 10:00 - 10:30 |
Keynote Talk: Cloud and Mobility: Disrupting the IP Ecosystem
 By Martin Lund
Senior Vice President, Research and Development, SoC Realization Group
Cadence
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| 10:30 - 11:00 |
Break |
| 11:00 - 11:30 |
Keynote Talk: Managing the IP Sourcing Process: an IDM Perspective
 By Philippe Quinio
Group Vice President of IP Sourcing & Strategy
STMicroelectronics
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| 11:30 - 12:00 |
Keynote Talk: 20nm Analog/Mixed-Signal IP: Business As Usual?
 By Joachim Kunkel
Senior Vice President and General Manager, Solutions Group
Synopsys
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| 12:00 - 12:30 |
Duopoly, Monopoly leading to Opportunity
 By Marc Miller
Sr. Director of Marketing
Tabula
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| 12:30 - 13:30 |
Lunch |
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AUDITORIUM |
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KILIMANDJARO |
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MONT BLANC |
| 13:30 - 15:30 |
Panel: IP in the cloud
Organizer:
 Omri Raisman
Panelists:
- Omri Raisman , Rosetta IP
- Steven J. Dovich, Cadence
- Marc Miller, Sr. Director of Marketing, Tabula
- Marcello Coppola, STMicroelectronics
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13:30 - 14:00 |
µfluidic applications: an upcoming Eldorado for µelectronic ?
By Dr Christine Peponnet
Head of Bio System on Chip Group
CEA Leti
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13:30 - 14:45
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Session 4: Hot Topics in SoC design
Chairman: Peter Hirt (STMicroelectronics)
-"Can your Enterprise IP management platform be tailored to satisfy the diverse requirements of Designers / Marketing / Sales /Procurement managers and keep everything in synch" by Gabriele Saucier (Design And Reuse)
-"Interface IP: winners and losers in 2012; thanks to mix of emerging and matures protocols getting traction, 5 years 10% CAGR expected" by Eric Esteve (IPNest)
-"How to make the Best Use of 3rd Party IP Market?" by Mohit Gupta (Open-Silicon Inc.)
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14:00 - 15:00 |
Session 1: IP Design
Chairman: Jean-Francois Pollet (Dolphin Integration)
-"Galois Field Low Power Inversion for Forward Error Correction in Highspeed Fiber Optic Communications above 40Gbit/sec" by SeshaGiri Rao M (Department of Electronics and Information Technology)
-"Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design" by Andrew Cole (Silicon Creations)
-"An efficient approach to evaluate Dynamic and Static voltage-drop on a multi-million transistor SoC design." by Abhishek Nigam (ST Microelectronics)
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14:45 -
15:00 |
Break |
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15:00
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Break
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15:00
- 16:15
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Session 4b: Hot Topics in SoC design
Chairman: Gert Goossens (Target Compiler)
-"Updating Design Challenges for Mobile SoC Design" by Jack Browne (Sonics Inc)
-"The Power of Developing Hardware and Software in Parallel" by Nithya Ruff, Andreas Ropers (Synopsys)
-"SoC Implementation-Driven Interconnect Design" by Gilles Baillieu (Arteris)
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| 15:30 - 16:00 |
Break |
15:30 - 16:30 |
Session 2: IP & Architecture Design
Chairman: Marcello Coppola (STMicroelectronics)
-"PCIe 3.0 Controller Case Study & the challenge of Gen3" by Rabih Eid (PLDA)
-"Design and Implementation of SD Host Controller IP Core" by Jose Simon, Deepu Krishnan, Krishnakumar Rao, Biju Oommen, Ravindra Kumar (Centre for Development of Advanced Computing, Thiruvananthapuram)
-"Hardware implementation of a synchronous and high performance Network on chip for SoC" by Trong-Trinh Dang, Thanh-Tung Nguyen (RMIT International University), Xuan-Tu Tran (College of Technology (UET-VNU))
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| 16:00 - 18:00
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Panel: Platform & Subsystem IP: Trends and Realities
Organizer:
 Hal Barbour
President
CAST
Panelists:
- Bill Finch, CAST
- Jack Browne, Senior Vice President of Marketing, Sonics
- Eric Esteve, IP Nest
- Peter Hirt, Director IP Sourcing, STMicroelectronics
- Martin Lund, Senior Vice President, Research and Development, SoC Realization Group, Cadence
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16:15 - 16:30 |
Break |
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16:30 - 17:00 |
Break |
16:30 - 18:00 |
Session 5: Challenges in IP Design methodology
Chairman: Paolo Pezzati (Cadence)
-"Design IP Faster: Introducing the C~ High-Level Language" by Matthieu Wipliez, Nicolas Siret (Synflow), Nicola Carta, Francesca Palumbo, Luigi Raffo (EOLAB)
-"State of RTL based design - is it time to move beyond?" by Karl Kaiser (Esencia Technologies)
-"Are we too hard for agile?" by Mike Bartley (Test and Verification Solutions), Francois Cerisier (Test and Verification Solutions)
-"Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC" by Syed Saif Abrar (IBM), Maksim Jenihhin (Tallinn Technical University)
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17:00 - 17:30 |
Session 3: IP Quality and reliability
Chairman: Huy-Nam Nguyen (BULL)
-"A Standards Based Approach to the Reliability Specification of IP Components" by Adrian Evans, Dan Alexandrescu, Enrico Costenaro (iRoC Technologies), Michael Nicolaidis (TIMA Laboratory)
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| 18:30 - 20:30 |
Join the French Café and enjoy
regional food, French wine and songs
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DAY 2: Wednesday December 5, 2012
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| 8:00 - 9:00 |
Breakfast and Registration |
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AUDITORIUM |
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KILIMANDJARO |
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MONT BLANC |
| 09:00 - 09:45 |
Keynote Talk: Power is now a Software Issue
 By Colin Walls
Mentor Graphics
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09:00 - 10:20 |
Session 6: FPGA SOC
Chairman: Eric Esteve (IP Nest)
-"A Redbox on an "All Programmable SOC"" by Rainer Fehr, Stefan Leuenberger (NetModule AG)
Duration: 20 minutes
Seminar: Programming the ZYNQ All Programmable SoC
Speaker:
- Uwe Gertheinrich, Xilinx
Duration: 1 hour
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| 09:45-
10:15 |
Break |
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| 10:15 - 12:00 |
Seminar: A Formal Approach to Low Power Verification
Speaker:
- Barbara Jobstmann, Senior Field Applications Engineer , Jasper Design Automation
- Frédéric Rocheteau, R&D manager, STMicrolectronics
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10:20 - 10:30 |
Break |
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10:30 - 12:00 |
Session 8: Verification
Chairman: Laurent Ducousso (STMicroelectronics)
-"An Example Verification Environment for Different Types of Processor Models" by Emrah Armagan (Ericsson Microelectronics), Laurent Dawance (ST-Ericsson), Funda Kutay, Ates Berna (Ericsson Microelectronics)
-"Accelerated Verification of SoC interconnects and subsystems using Discovery™ VIP for the ARM® AMBA®4 protocol" by Fabian Delguste (Synopsys)
-"SoC Interconnect Verification Challenge" by François Cerisier, Mike Bartley (Test and Verification Solutions)
-"Supporting hardware assisted verification with synthesizable assertions" by Marcin Kubica (The University of Bielsko-Biala), Wlodziemierz Wrona (Evatronix SA), Wojciech Sakowski (Silesian University of Technology)
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10:30 -
12:00 |
Seminar: Parallel Computing
Organizer:
 Huy-Nam Nguyen
BULL
Speaker:
- Gert Goossens, CEO , Target Compiler Technologies
- Franck Wajsburt, UPMC/Lip6
- Huy-Nam Nguyen, BULL
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| 12:00 - 13:00 |
Lunch |
12:00 - 13:00 |
Lunch |
12:00 - 13:00 |
Lunch |
| 13:00 - 14:30 |
Seminar: Faster and safer design for integration of power-optimized SoCs
Speaker:
- Sebastien Genevey, CTO for analog developments, Dolphin Integration
- Lucille Engels, Development Manager for the SoC Integration Product Line, Dolphin Integration
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13:00 -
14:30 |
Session 9: Verification
Chairman: Gabriele Zarri (Cadence)
-"Building a UVM Verification Environment for ARM ACE SoCs" by Mirit Fromovich (Cadence Design Systems)
-"Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence" by Rich Edelman Alain Gonier (Mentor Graphics)
-"Extraction methods of vocal characteristics for Embedded Systems" by Elmar Melcher, Joseana Fechine, Elton Costa, Mikhail Barros, Victor Perone (UFCG)
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13:00 -
14:30 |
Seminar: Challenges and solutions in IP management
Organizer:
Gabriele Saucier
CEO
Design And Reuse
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