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DAY 1: Wednesday November 6, 2013
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| 08:00 - 09:15 |
Breakfast and Registration
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AUDITORIUM |
| 09:15 - 09:45 |
Keynote Talk: IP Business: Status and Perspectives
 By Gabriele Saucier
CEO
Design And Reuse
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| 09:45 - 10:15 |
Keynote Talk: The competitive landscape of the Semiconductor IP Market, 2013 and Beyond!
 By Ganesh Ramamoorthy
Research Director
Gartner Inc.
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| 10:15 - 10:30 |
Break |
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Chairman: Patrick Blouet
(STMicroelectronics) |
| 10:30 - 11:00 |
Keynote Talk: Open Innovation Platform (OIP): an ecosystem for innovation
 By Kees Joosse
Business Development Manager
TSMC
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| 11:00 - 11:30 |
Keynote Talk: SMIC Foundry's View
 By Tian ShenTang
Senior VP
SMIC
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| 11:30 - 12:00 |
Keynote Talk: FD-SOI technology for energy efficient SoCs: IP development examples
 By Giorgio Cesana
Director of Marketing and Communications
STMicroelectronics
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| 12:00 - 13:00 |
Lunch |
13:00 - 13:30
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Keynote Talk: Morphing Technology and Business Models at 100Gbps and Beyond
 By Marc Miller
Sr. Director of Marketing
Tabula
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| 13:30 - 14:00 |
Keynote Talk: The flexible pathway to Flash IP
 By Christopher Neil Brown
Silicon Storage Technology
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| 14:00 - 14:15 |
Break |
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AUDITORIUM |
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KILIMANDJARO |
14:15 - 14:45
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Keynote Talk: The challenges of Third Party IP Management infrastructure
By Gabriele Saucier
CEO
Design And Reuse
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14:15 - 14:45 |
Keynote Talk: The challenges of integrating high performance Inertial Measurement Unit (IMU)
 By Christian Domingues
Dolphin Integration
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| 14:45 - 15:45 |
Session 1: IP Business and Trends
Chairman: Philippe Quinio, Group Vice President of IP Sourcing & Strategy (STMicroelectronics)
-"The MVP of IP Cores" by Gerardo Nahum, Omri Raisman (Rosetta IP)
-"Perceptual Mapping for Newly Developed 3rd Party IP" by Sanjeev Sharma (Terminus Circuits) 
-"Moving PCI Express to Mobile (M-PCIe)" by Richard Solomon (Synopsys)
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14:45 - 15:45 |
Session 4: IP Design
Chairman: Paolo Pezzati (Cadence)
-"Scalable Architectures for Analog IP on Advanced Process Nodes" by Manuel Mota (Synopsys)
-"A Clock Tree Synthesis Flow Tailored for Low Power" by Arzu Datli, Umut Eksi, Gokhan Isik (Ericsson)
-"Auto Clock Generation for a SoC" by Mrugesh Walimbe, Mahesh Penugonda (Open-Silicon)
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| 15:45 - 16:00 |
Break
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| 16:00 - 17:00 |
Session 2: Best IP Practice
Chairman: Omri Raisman (Rosetta IP)
-"Using IP-XACT Metadata for a TLM modeling Flow" by Jack Donovan, Edwin Dankert (Duolog Technologies)
-"IP Exchange Through Handoff for Easy System-On-Chip Design" by Rahul Kheterpal, Atul Nauriyal, Vivek Sinha (STMicroelectronics Pvt.Ltd)
-"Design Rights Management of Intellectual Property (IP) Cores in SoPC designs" by Jerome Rampon, Renaud Perillat-Amédée, Gael Paul (Algodone), Lionel Torrès (Université Montpellier 2)
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16:00 -
17:00 |
Session 5: From IP to System On Chip Architecture
Chairman: Marc Miller (Tabula)
-"A design methodology using Power-Grid Prototyping to optimize Area Performance of SoCs" by Abhishek Nigam (STMicroelectronics Pvt. Ltd), Anant Narain (Apache Design Solutions (a sub. of ANSYS Inc.))
-"Display Driver with on-chip Full-HD frame buffer and a scalable image compression Codec" by Star Sung, Blue Lan, Jacques Baudier (TITC-USA)
-"Performance analysis of 8-bit pipelined Asynchronous Processor core" by Yasha Jyothi M Shirur, Veena S Chakravarthi, Gourav Thakur (BNM Institute of Technology)
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| 17:00 - 17:15 |
Break
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AUDITORIUM |
| 17:15 - 17:30 |
Keynote Talk: The power of eco-systems
 By Patrick Blouet
Collaborative Program Manager
STMicroelectronics
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| 17:30 - 18:00 |
Keynote Talk: NoC Power-Management Advantages
 By Drew Wingard
CTO
Sonics
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| 18:00 - 18:30 |
Keynote Talk: Internet on Things
 By Jauher Zaidi
Chairman
Palmchip, Netvinci, Moobila
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| 19:00 - 19-15 |
Best IP SoC Prize and Refreshments
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| 19:00 - 20:30 |
Join the "French Touch" party and enjoy regional food
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DAY 2: Thursday November 7, 2013
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| 08:00 - 09:00 |
Breakfast and Registration |
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AUDITORIUM |
| 09:00 - 09:25 |
Keynote Talk: Embedded design in the Age of Pervasive Computing
 By Richard York
Director of Embedded Processor Products
ARM
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| 09:25 - 09:50 |
Keynote Talk: Virtual Prototyping - A Reality Check
 By Johannes Stahl
Director, Product Marketing, System-Level Solutions
Synopsys
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09:50 - 10:15
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Keynote Talk: The New Tower of Babel - The Languages of Embedded Systems Design
 By Colin Walls
Mentor Graphics
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| 10:15 - 10:30 |
Break |
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AUDITORIUM |
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KILIMANDJARO |
| 10:30 - 12:00 |
Session 6: Embedded Systems
Chairman: Colin Walls (Mentor Graphics)
-"Architectural Capabilities of Multicore Operating Systems" by Serge Plagnol (Green Hills Software)
-"Self-testing in Embedded Systems" by Colin Walls (Mentor Graphics)
-"Embedded Security - Protection with Performance Using Hardware IP" by Bart Stevens (INSIDE Secure)
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10:30 - 12:00 |
Session 8: System Optimization, Simulation and Verification
Chairman: Dr. Johannes Stahl, Director, Product Marketing, System-Level Solutions (Synopsys)
-"Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL" by Syed Saif AbrarR (IBM), MAKSIM JENIHHIN, JAAN RAIK (TUT)
-"End-to-End Simulation of Network-based Computing Systems" by Nguyen Tuan Anh (Bull/UPEC), Nguyen Huy Nam (Bull), Amir Nakib, Eric Petit (UPEC)
-"Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP" by Srikanth Vadanaparthi, Shekhil Hassan (Synopsys India Pvt. Ltd.)
-"CPF Based Verification of an SoC - Lessons Learnt" by Baris Guven, Levent Cetrez (Ericsson Microelectronics Design Center)
-"Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP" by Shalini Damani, Sunny Aggarrwal (Freescale Semiconductor)
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| 12:00 - 13:00 |
Lunch |
| 13:00 - 15:00 |
Session 7: Embedded Core to Multi Processor
Chairman: Drew Wingard, CTO (Sonics)
-"Forward-Looking SoC-based PHY Architecture for Macro and Small Cell LTE eNode-Bs" by Venkatasubramanian Viraraghavan, Kulandaivel.P Palani, Dimitri Dey (Tata Consultancy Services)
-"RISC-VLIW IP Core for the Airborn Navigation Functional Oriented Processor" by Nick Lookin (Ural Federal University), Serge Shestakov (Institute of Engineering Sciences), Bersenev Vadim (Ural Division of RAS) ,
-"Next Generation Wireless IP for the Internet of Things" by Narasimhan Venkatesh (Redpine Signals)
-"A novel soft interrupt routing mechanism for multiprocessor architectures" by Vasant Easwaran (Texas Instruments)
-"Plug-n-play UVM Environment for Verification of Interrupts in an IP " by Shalini Damani, Tejbal Prasad (Freescale Semiconductor)
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13:00 -
14:30 |
Session 9: Test, Simulation and Verification
Chairman: Huy-Nam Nguyen (BULL)
-"Acceleration Based Verification: New experiments" by Surinder Sood, Mahalakshmi Krishnan (Samsung Research India- Bangalore)
-"StripeViewer – Using Transactions to Effectively Debug Large SoC Designs" by Rich Edelman, Alain Gonier (Mentor Graphics)
-"Reusable Test-Case Methodology for SoC Verification" by Ganesh Venkatakrishnan (Open-Silicon)
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14:30 - 15:00 |
Seminar: New Generation IP Management Enterprise Platform: Why should companies outsource?
Organizer:
Gabriele Saucier
CEO
Design And Reuse
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| 15:00 - 15:15 |
Break |
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AUDITORIUM |
| 15:15 -
16:15 |
Panel: Challenges in Multi-Processor SoCs for mid-range applications
Moderator:
 Hal Barbour
President
CAST
Panelists:
- Richard York, ARM
- Colin Walls, Mentor
- Matjaz Breskvar, Beyond Semi
- Philippe Quinio, STMicroelectronics
- Nikos Zervas, CAST
- Wojtek Sakowski, Cadence
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| 16:15 - 16:30 |
Lucky Draw |
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