IP-SOC 2013
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DAY 1: Wednesday November 6, 2013

08:00 - 09:15 Breakfast and Registration

09:15 - 09:45 Keynote Talk: IP Business: Status and Perspectives

By Gabriele Saucier
Design And Reuse

09:45 - 10:15 Keynote Talk: The competitive landscape of the Semiconductor IP Market, 2013 and Beyond!

By Ganesh Ramamoorthy
Research Director
Gartner Inc.

10:15 - 10:30 Break

Chairman: Patrick Blouet (STMicroelectronics)
10:30 - 11:00 Keynote Talk: Open Innovation Platform (OIP): an ecosystem for innovation

By Kees Joosse
Business Development Manager
View Slides

11:00 - 11:30 Keynote Talk: SMIC Foundry's View

By Tian ShenTang
Senior VP

11:30 - 12:00 Keynote Talk: FD-SOI technology for energy efficient SoCs: IP development examples

By Giorgio Cesana
Director of Marketing and Communications
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12:00 - 13:00 Lunch
13:00 - 13:30
Keynote Talk: Morphing Technology and Business Models at 100Gbps and Beyond

By Marc Miller
Sr. Director of Marketing
View Video

13:30 - 14:00 Keynote Talk: The flexible pathway to Flash IP

By Christopher Neil Brown
Silicon Storage Technology

14:00 - 14:15 Break

14:15 - 14:45
Keynote Talk: The challenges of Third Party IP Management infrastructure

By Gabriele Saucier
Design And Reuse

14:15 - 14:45 Keynote Talk: The challenges of integrating high performance Inertial Measurement Unit (IMU)

By Christian Domingues
Dolphin Integration
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14:45 - 15:45 Session 1: IP Business and Trends
Chairman: Philippe Quinio, Group Vice President of IP Sourcing & Strategy (STMicroelectronics)

-"The MVP of IP Cores" by Gerardo Nahum, Omri Raisman (Rosetta IP)

-"Perceptual Mapping for Newly Developed 3rd Party IP" by Sanjeev Sharma (Terminus Circuits) View Slides

-"Moving PCI Express to Mobile (M-PCIe)" by Richard Solomon (Synopsys) View Slides

14:45 - 15:45 Session 4: IP Design
Chairman: Paolo Pezzati (Cadence)

-"Scalable Architectures for Analog IP on Advanced Process Nodes" by Manuel Mota (Synopsys) View Slides

-"A Clock Tree Synthesis Flow Tailored for Low Power" by Arzu Datli, Umut Eksi, Gokhan Isik (Ericsson) View Slides

-"Auto Clock Generation for a SoC" by Mrugesh Walimbe, Mahesh Penugonda (Open-Silicon) View Slides

15:45 - 16:00 Break
16:00 - 17:00 Session 2: Best IP Practice
Chairman: Omri Raisman (Rosetta IP)

-"Using IP-XACT Metadata for a TLM modeling Flow" by Jack Donovan, Edwin Dankert (Duolog Technologies) View Slides

-"IP Exchange Through Handoff for Easy System-On-Chip Design" by Rahul Kheterpal, Atul Nauriyal, Vivek Sinha (STMicroelectronics Pvt.Ltd) View Slides

-"Design Rights Management of Intellectual Property (IP) Cores in SoPC designs" by Jerome Rampon, Renaud Perillat-Amédée, Gael Paul (Algodone), Lionel Torrès (Université Montpellier 2) View Slides

16:00 - 17:00 Session 5: From IP to System On Chip Architecture
Chairman: Marc Miller (Tabula)

-"A design methodology using Power-Grid Prototyping to optimize Area Performance of SoCs" by Abhishek Nigam (STMicroelectronics Pvt. Ltd), Anant Narain (Apache Design Solutions (a sub. of ANSYS Inc.)) View Slides

-"Display Driver with on-chip Full-HD frame buffer and a scalable image compression Codec" by Star Sung, Blue Lan, Jacques Baudier (TITC-USA) View Slides

-"Performance analysis of 8-bit pipelined Asynchronous Processor core" by Yasha Jyothi M Shirur, Veena S Chakravarthi, Gourav Thakur (BNM Institute of Technology) View Slides

17:00 - 17:15 Break

17:15 - 17:30 Keynote Talk: The power of eco-systems

By Patrick Blouet
Collaborative Program Manager
View Slides

17:30 - 18:00 Keynote Talk: NoC Power-Management Advantages

By Drew Wingard
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18:00 - 18:30 Keynote Talk: Internet on Things

By Jauher Zaidi
Palmchip, Netvinci, Moobila
View Slides

19:00 - 19-15 Best IP SoC Prize and Refreshments
19:00 - 20:30 Join the "French Touch" party and enjoy regional food

DAY 2: Thursday November 7, 2013

08:00 - 09:00 Breakfast and Registration

09:00 - 09:25 Keynote Talk: Embedded design in the Age of Pervasive Computing

By Richard York
Director of Embedded Processor Products

09:25 - 09:50 Keynote Talk: Virtual Prototyping - A Reality Check

By Johannes Stahl
Director, Product Marketing, System-Level Solutions
View Slides

09:50 - 10:15
Keynote Talk: The New Tower of Babel - The Languages of Embedded Systems Design

By Colin Walls
Mentor Graphics
View Video
View Slides

10:15 - 10:30 Break

10:30 - 12:00 Session 6: Embedded Systems
Chairman: Colin Walls (Mentor Graphics)

-"Architectural Capabilities of Multicore Operating Systems" by Serge Plagnol (Green Hills Software)

-"Self-testing in Embedded Systems" by Colin Walls (Mentor Graphics) View Slides

-"Embedded Security - Protection with Performance Using Hardware IP" by Bart Stevens (INSIDE Secure)View Slides
View Video

10:30 - 12:00 Session 8: System Optimization, Simulation and Verification
Chairman: Dr. Johannes Stahl, Director, Product Marketing, System-Level Solutions (Synopsys)

-"Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL" by Syed Saif AbrarR (IBM), MAKSIM JENIHHIN, JAAN RAIK (TUT)

-"End-to-End Simulation of Network-based Computing Systems" by Nguyen Tuan Anh (Bull/UPEC), Nguyen Huy Nam (Bull), Amir Nakib, Eric Petit (UPEC)View Slides

-"Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP" by Srikanth Vadanaparthi, Shekhil Hassan (Synopsys India Pvt. Ltd.)

-"CPF Based Verification of an SoC - Lessons Learnt" by Baris Guven, Levent Cetrez (Ericsson Microelectronics Design Center) View Slides

-"Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP" by Shalini Damani, Sunny Aggarrwal (Freescale Semiconductor) View Slides

12:00 - 13:00 Lunch
13:00 - 15:00 Session 7: Embedded Core to Multi Processor
Chairman: Drew Wingard, CTO (Sonics)

-"Forward-Looking SoC-based PHY Architecture for Macro and Small Cell LTE eNode-Bs" by Venkatasubramanian Viraraghavan, Kulandaivel.P Palani, Dimitri Dey (Tata Consultancy Services)

-"RISC-VLIW IP Core for the Airborn Navigation Functional Oriented Processor" by Nick Lookin (Ural Federal University), Serge Shestakov (Institute of Engineering Sciences), Bersenev Vadim (Ural Division of RAS) , View Slides

-"Next Generation Wireless IP for the Internet of Things" by Narasimhan Venkatesh (Redpine Signals) View Slides

-"A novel soft interrupt routing mechanism for multiprocessor architectures" by Vasant Easwaran (Texas Instruments) View Slides

-"Plug-n-play UVM Environment for Verification of Interrupts in an IP " by Shalini Damani, Tejbal Prasad (Freescale Semiconductor) View Slides

13:00 - 14:30 Session 9: Test, Simulation and Verification
Chairman: Huy-Nam Nguyen (BULL)

-"Acceleration Based Verification: New experiments" by Surinder Sood, Mahalakshmi Krishnan (Samsung Research India- Bangalore) View Slides

-"StripeViewer – Using Transactions to Effectively Debug Large SoC Designs" by Rich Edelman, Alain Gonier (Mentor Graphics) View Slides

-"Reusable Test-Case Methodology for SoC Verification" by Ganesh Venkatakrishnan (Open-Silicon) View Slides

14:30 - 15:00 Seminar: New Generation IP Management Enterprise Platform: Why should companies outsource?

Gabriele Saucier
Design And Reuse

15:00 - 15:15 Break

15:15 - 16:15 Panel: Challenges in Multi-Processor SoCs for mid-range applications

Hal Barbour

- Richard York, ARM
- Colin Walls, Mentor
- Matjaz Breskvar, Beyond Semi
- Philippe Quinio, STMicroelectronics
- Nikos Zervas, CAST
- Wojtek Sakowski, Cadence

16:15 - 16:30 Lucky Draw

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