The challenges of Third Party IP Management infrastructure
By Gabriele Saucier,
Design And Reuse
Gabriele Saucier received her PhD from the University of Grenoble, where she was a professor and headed a research lab on Integrated System Design. She has published more than 350 papers in the design and EDA fields. Dr. Saucier is an IEEE fellow for her contributions in synthesis, test generation and fault tolerance. Leaving her university career, in the 1990s she founded a synthesis company, IST (Innovative Synthesis Technologies), mainly dedicated to FPGA synthesis, and in 1997 Design and Reuse, dedicated to IP-based design. She has launched two successful conferences - Euroasic and IP/SoC.