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Voltage Monitor with Digital Output TSMC N5P (Multi-domain supply monitoring)
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Conference Program |
Advisory Board |
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Practical Information |
DAY 1: IP SoC Day - Wednesday December 2, 2015
| 08:00 - 09:00 | Breakfast and Registration |
| 09:00 - 09:20 | Innovation the vital Seed of electronics Industry By Gabriele SaucierCEO Design And Reuse |
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Foundry Corner and Innovation in
Technology Chairman: Gabriele Saucier, Design And Reuse |
| 09:20 - 09:50 | Smic's IP Platform and Design Services By Hongying WuSr Director of IP Alliance Program SMIC |
| 09:50 - 10:20 | FDSOI is taking on speed as platform and a European focus project By Gerd TeepeGlobalFoundries |
| 10:20 - 10:55 | Break |
| 10:55 - 11:15 | FDSOI IP Shop: The key enabler of success By Patrick BlouetCollaborative program manager STMicroelectronics  |
| 11:15 - 11:35 | FD-SOI a New Era for Power Efficiency: Why and How? By Olivier ThomasSilicon Impulse, CEA - LETI |
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IP and Automotive Market
Chairman: Drew Wingard, Sonics |
| 11:35 - 12:00 | Automotive Electronics By Marco VrouweTSMC |
| 12:00 - 12:15 | The IP Market for Automotive - A Suppliers Perspective By Claude GauthierOmniPhy |
| 12:15 - 13:15 | Lunch |
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IP SoC Strategies and Vision
Chairman: Mark Ma, Shanghai Jiatao Industrial |
| 13:15 - 13:35 |
Strategies for SoC / IP Design for Emerging Applications:An Indian perspective By Samir PatelSankalp Semiconductor |
| 13:35 - 13:55 |
Assessing and managing the IP Sourcing Risk By Philippe QuinioSTMicroelectronics |
| 13:55 - 14:15 | Semiconductor Industry Consolidation Wave: What is left for IP Companies By Sanjeev Kumar SharmaTerminus Circuits |
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IP Ecosystem
Chairman: Philippe Quinio, STMicroelectronics |
| 14:15 - 14:35 | Irrationality in IP Ecosystem By Shine ChungAttopSemi |
| 14:35 - 14:55 | Customized IP rather than Customizable IP By Sujoy ChakrabortySilabtech |
| 14:55 - 15:15 | A Standard D&R IP Provider Station By Gabriele Saucier CEO Design And Reuse |
| 15:15 - 15:35 | Why Embedded NVM is an Important Part of Every SoC By Xerxes WaniaSidense  |
| 15:35 - 16:00 | Break |
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Technical Highlights in Power Optimization
Chairman: Alexandre Valentian, CEA |
| 16:00 - 16:20 |
Power Planning and Timing Signoff Solutions By Jean-Luc PelloieARM |
| 16:20 - 16:40 | Autonomous Power Subsystem IP By Drew WingardSonics |
| 16:40 - 17:00 | The DELTA breakthrough: the standard for embedding power management systems By Didier MaurerDolphin Integration |
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Standards and Innovation in IP Design
Chairman: Samir Patel, Sankalp Semiconductor |
| 17:00 - 17:20 | Increasing Effectiveness of LTE and WiFi Applications, Seamlessly By Roger YangSeamless Devices |
| 17:20 - 17:40 | Reusable MAC Design for Various Wireless Connectivity Protocols By Sangho Seo, Gyongsu LeeNewracom |
| 17:40 - 18:00 | High performance customizable DDR PHY By Nidhir KumarKrivi Semiconductor |
| 18:20 - 20:00 | Reception Dinner |
DAY 2: Embedded Systems Day - Thursday December 3, 2015
| 08:00 - 09:00 | Breakfast and Registration |
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Embedded Systems Chairman: Colin Walls, Mentor Graphics |
| 09:00 - 09:30 | Embedded Software is Everywhere By Colin WallsMentor Graphics |
| 09:30 - 09:50 | Design Challenges for Security By Gregory BaudetBarco Silex |
| 09:50 - 10:15 | Break |
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Tool License Management Chairman: Patrick Blouet, STMicroelectronics |
| 10:15 - 10:45 | Optimize your Tool license management : A platform integrating administration, finance and monitoring views By Gabriele Saucier CEO Design And Reuse |
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What's special on FPGA
Chairman: Eric Esteve, IP Nest |
| 10:45 - 11:05 | What an FPGA Vendor Knows about IP Reuse By Ron WilsonAltera |
| 11:05 - 11:20 | Handling external IP in FPGA-based Prototyping By Huy-Nam NguyenAtos |
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Verification Session 1
Chairman: Pankaj Singh, Infineon |
| 11:20 - 11:50 | IP Signoff with Code Complexity By Sylvain DanjeanDefacto Technologies |
| 11:50 - 12:20 | Modeling & Verification of Mixed Signal IP using SystemVerilog in Virtuoso & NCsim By Tom ThomasSilabTech |
| 12:20 - 13:20 | Lunch |
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Verification Session 2
Chairman: Huy-Nam Nguyen, Atos |
| 13:20 - 13:40 | Meeting Functional Verification & Safety Verification Goals for Advances SoC Designs By Pankaj SinghInfineon |
| 13:40 - 14:00 | Verification Framework for IO Accelerators using SV Models By Ajay BSVeriedge Technologies |
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Internet of Things Chairman: Nikos Zervas, CAST |
| 14:00 - 14:20 | IP That Will Drive Energy-Efficient IoT Designs By Philippe BorgesField Applications Engineer Synopsys |
| 14:20 - 14:40 | Making IoT Security a Reality By Bart StevensDirector of Product Management, Mobile and Networking Hardware Security Solutions Inside Secure |
| 14:40 - 15:00 | Innovative Energy Savings Using GZIP IP Within IoT Devices By Nikos ZervasCEO CAST |
| 15:00 - 16:30 | Panel: The impact of IoT on IP Program Moderator:  Hal BarbourChairman CAST Panelists: - Nikos Zervas, CAST - Bart Stevens, Inside Secure - Philippe Borges, Synopsys - Philippe Quinio, STMicroelectronics - Matjaz Breskver, Beyond Semiconductor |
| 16:30 - 16:45 | Lucky Draw |