Irrationality in IP Ecosystem
By Shine Chung,
Shine Chung received his B.S. in Physics from National Taiwan University, MSEE in Electronics from National Chiao-Tung University, and MS in Applied Physics from Harvard University.
Since 1981, he worked in the semiconductor industry. From 1982 to 1984, he worked for AMD in SRAM technology development and SRAM design. Then he worked for VLSI Design Associate in ASIC logic and memory design. He also worked for HP Labs in PA-WW Architecture, precedent of Merced Architecture, from 1989 to 1994. After leaving HP, he worked as an Architecture Group Manager on StrongARM 1500 for Digital and as logic designer on the low power K5 microprocessor for AMD. He was also a System Architect at Intel, responsible for mobile CPU roadmap. In year 1999, he was a VP of Engineering, CTO, and co-founder of Audia Technology, specializing in digital hearing aid ICs and devices. Then, he worked for TSMC as a Director in memory related IP development from 2003 to 2010. Currently, he is the Chairman of a semiconductor IP company Attopsemi Technology Co.
Mr. Chung is a two-time TSMC corporate innovation award recipient from 2007-2008. He was in the ISSCC technical program committee from 2007-2010, and VLSI Circuit Symposium from 2009-2010. He frequently gave talks in tutorial, forum, and panel in IEEE SOC, ISSCC, and VLSI Symposium. He has more than 61 U. S. patents granted before founding Attopsemi and filed more than 60 U.S. patents afterward