FD-SOI a New Era for Power Efficiency: Why and How?
By Olivier Thomas,
Silicon Impulse, CEA - LETI
Olivier THOMAS received the M.S. Electrical Engineering degree in 2001 and the Ph.D. degree in microelectronics in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. He was first involved in the development of low-power and low-leakage design solutions for digital wireless applications in 65nm Partially-Depleted SOI technology in collaboration with STMicroelectronics. From 2006 to 2010, he was in charge of low power SRAM and Digital design projects in Thin Film SOI technologies. His work was focused on efficient and simple multiple-VT design solutions. From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. Back to CEA-LETI, from 2012 to 2014, he launched and led a advanced memory design group at LETI. Since January 2015 he is the project leader of Silicon Impulse an IC competence center helping companies to design innovative products based on the latest low-power semiconductor technologies. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.