VIA PUF: Ultimately Stable PUF Design using Random Via Formation in Standard CMOS Technology
By Jein Yu,
In this paper, a novel approach for very stable physical unclonable function (PUF) is presented based on randomly generated via-hole formation using standard CMOS process. Recently, various types of PUF technologies have been presented. However, because of the low reliability, which is the major drawback of conventional PUFs, complicated post processing to reduce bit error rate (BER) is indispensable.
To achieve 0% BER, VIA-PUF was proposed using the probability of physical connection between the electrical layers. The via is a vertical connection between two metal layers in integrated circuits. To guarantee this connection, IC manufacturers establish a design rule regulating the minimum via hole size. Accordingly, if the via hole size is designed smaller than the given design rule, its connection is uncertain. The advantages of using via holes are that the open or short states in the circuit create very clear voltage or current differences, and once the open or short states are determined, they are not changed over time due to certain environmental noise without a heavy post-processing such as error correction.
The VIA-PUF response can be easily extracted from a read transistor with grounded-gate PMOS as a resistive load. The via for a PUF is placed between them. In this work, we tried various via hole sizes, and 20,480 via holes are designed for each size. Post processing may be applied to increase the entropy rate and uniformity of the output bit sequence.
From the experimental results with the fabricated chips in a 0.18 Î¼m CMOS process, we found the VIA-PUF has 51.12% uniformity and 49.64% uniqueness, and 0% BER throughout 1,000-time repeated measurements. Especially, we have no bit change after the stress test at 25 and 125 ÂºC for 96 hours.