Unified Methodology for effective correlation of SoC Power Estimation and Signoff
By Pankaj Singh, Girish Ravandur Chikkaveerappa, Edwin Darmawan Marelie, Lalit Gohate,
As SoC increases in complexity, one of the elements that are becoming critical is effective power estimation and correlation with silicon. Early and accurate SoC power estimation is becoming a challenge. Using traditional flow, an accurate power assessment cannot be guaranteed until gate level netlist after timing closure is available. This can lead to late design changes. The issue is exacerbated if the power measurements do not correlate well with silicon leading to costly design re-spins.
While the tool for early power estimation has matured, there is no comprehensive methodology to provide complete end to end solution for accurate power estimates and correlation with silicon measurements. After the silicon arrives, it takes significant effort to debug any issues related to power measurements / correlation, often requiring multiple iterations of test code delivery between pre- and post-silicon team. It is imperative to develop robust methodology that provides unified framework across pre and post silicon domains for accurate power estimations and correlations.
In this paper, we present unified methodology to overcome these limitations. The methodology presented in this paper allows early and accurate power estimation at RTL stage, minimizing late change in architecture design. Besides creating test for typical power scenario as per specification we also look at real customer use case scenario. These early power estimates are compared with the gate level netlist.
Common test framework provides unique ability to maximize reuse of test environment and patterns across different platforms. It avoids multiple deliveries to meet specific test platform requirements. It saves wasteful and difficult debug effort between pre- and post-silicon teams leading to regeneration of patterns due to environment or setup issues.
This methodology resulted in early silicon bring-up as issues observed in silicon can be reproduced in pre-silicon SoC verification environment for quick debug and regeneration of patterns. The same test framework is used across Production and Characterization test platforms with minimal changes related to tester setup.
Complete process is requirement driven and automated minimizing manual effort or error, enabling traceability of requirements thereby improving the overall quality and time. It also includes innovative approach for the development and simulations of a complex power pattern at SoC level of Automotive Microcontrollers as described in the presentation.
This paper is organized in different sections. The first section describes the complete end to end power estimation, measurement, and correlation flow. The next section goes into the details of Unified Power Pattern Methodology. It starts with the overview of Unified SoC Methodology and expands on each stage of this methodology. Simple diagrams are used for easy understanding of different stages starting from customer requirements to development of environment. The common elements of SoC Power Pattern Code environment and their functionality are explained in this section. The specific setup across each platform i.e. Pre-Si power estimation to 1st silicon bring-up, validation, production and characterization tester is also explained in this paper. Final section includes correlation results and highlights the benefits of this methodology.
Pankaj completed his Bachelors in Electronics from NIT Bhopal in 1993; Master's in Electrical Engineering from USF, Florida and an MBA from SMU, Dallas.
He has 20 years of industry experience which includes various leadership management roles.
Currently he is leading Infineon's Automotive SoC verification division in Singapore.
He has published 27 technical papers in various international conferences on design implementation-verification topics such as Synthesis, DFT, Analog IP integration and functional Verification.