Hybrid hardware architecture for low complexity motion estimation algorithm
By Anil Celebi,
Nowadays hybrid hardware architecture (HHA) becomes increasingly popular in embedded systems (ES). In this paper HHA is presented for low bit depth motion estimation (ME) algorithm. Intellectual property (IP) core is designed for ME algorithm by using field programmable gate array (FPGA) and this IP is integrated with processor system (PS) to investigate its performance in an ES. Designed ME based IP has data bus of size 32bits and is working properly up to 200 MHz. Experiments show that the HHA is integrated successfully and gives expected results in real time.
Anil Celebi was born in Ordu, Turkey. He received the B.Sc., M.Sc. and Ph.D. degrees in Electronics and Communication Engineering from Kocaeli University, Kocaeli, Turkey, in 2002, 2005, and 2008, respectively. Since 2002 he has been with the Department of Electronics and Telecommunications Engineering, University of Kocaeli, Turkey. He worked as a BK21 Post Doctoral Research fellow at the School of Electrical Engineering and Computer Science at Seoul National University, Korea between April - July 2009. His research interests include very large scale integration (VLSI) design and implementation for analog/mixed signal systems, image processing and video coding systems.
He is currently working as an Assistant Professor at the Department of Electronics and Telecommunications Engineering, University of Kocaeli, Turkey. He is also founder of KuanTek Electronics and Information Technologies Ltd (www.kuantek.com.tr).