A 4-MHz parameterized Logarithm-Square Root IP-Core
By Elton Costa,
Logarithms and square root are non-elementary operations frequently used in digital signal processing. In this work, implementation and design of an IP-Core to compute square root and multibase logarithm is presented. The design is parameterized in fixed point notation achieving a low arithmetic error even when irrational numbers are being calculated. The module was synthesized in ASIC using FSC0G D GENERIC CORE from UMC and in FPGA occupying 518 logic elements and two DSP blocks for multiplication.