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SerDes in High-Reliability, Long Reach Systems
By Claude Gauthier, Director of Engineering, Mosys

Overview:

The presentation explores the challenges facing designers implementing systems that are compliant to 10GBASE-KR and CEI11-LR standards. These systems can be 40-50 with multiple connectors and it is desirable to have bit-error-rates (BER) of 10-15 to 10-18 for high-reliability applications, going beyond the specification for these real-world channels. A system model is described and representative channels are presented. The paper explores the architectural and circuit techniques required to meet the stringent requirements, including the trade-offs associated with PLL implementation and receiver equalization. The LC PLL performance (<400fs) is shown to enable high-reliability system design.

Biography:

Claude Gauthier was born in Toronto Canada in 1973. He received the MS and PhD degrees in electrical engineering from the University of Michigan Ann Arbor in 1997 and 1999, respectively.

In 1999 he joined Sun Microsystems were he lead the implementation of IO and Global Circuits for the UltraSparc V microprocessor, leaving to join ATI in 2004. At ATI he developed PCIE and GDDR5 interfaces and saw his first silicon shipping in very high volume. In 2007 he joined Prism Circuits, a start-up focused on high-speed SerDes IP. The company was acquired by MoSys in June of 2009.

Dr Gauthier is currently managing the implementation of a low-power 10GBase-KR SerDes in TSMC's 28nm technology. He has 12 publications, holds over 80 issued US Patents, and has been a frequent guest lecturer at both ISSCC and Stanford University.