IP/SOC Days

Dresden Event >>

March 14, 2016

Bangalore Event >>

April, 2017

Shanghai Event >>

September 14, 2017

Grenoble Event >>

December 6-7, 2016

USB 3 and 10G Ethernet Switch IP
By Kash Johal, CEO, SiliconIP and Services

Overview:

SiliconIP and Services is introducing two new IP cores to market at DAC. The FIRST low latency Ethernet layer 2 switch IP core with non blocking bandwidth of 160G (up to 16 x 10G ports max) on FPGA's and 320G (up to 32 x 10G ports max ) on ASIC. The IP core is optimized for low latency with sub 80 ns latency from port to port. USB 3.0 superspeed core optimised for FPGA and ASIC use and low cost. It will be demonstrated on a Xilinx spartan 6 development board.