Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory

Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory

Grenoble, France – April 9, 2018 -- Dolphin Integration, leader in innovative design solutions for the next generation of Energy-Efficient System-on-Chips, augments TSMC’s IP ecosystem at 40 nm with TITAN, a breakthrough architecture for Read Only Memory compiler. This cost effective, single-layer and late programmable ROM compiler is capable of generating instance sizes from 512 bits to 1 Mbits. It is immediately available for evaluation on your private space, MyDolphin.

This 40 nm ULP eFlash ROM compiler, based on the TITAN architecture, combines high-density with ultra-low power consumption. This innovative architecture has already been silicon proven in 55 nm and 90 nm process technologies. The TITAN ROM compiler reduces fabrication costs and time-to-market as programming is performed using only the metal 1 layer. Configurable multiplexer option, from 8 to 128, provides designers with the flexibility to select a ROM configuration to meet the target performances with the optimal floorplan. The online ROM compiler allows the designer to quickly complete an objective performance assessment. It automatically generates datasheets, simulation (Verilog), layout (GDSII), footprint (LEF), timing/power (Liberty) and MBIST (Tessent) models. “

“There are a number of applications which still embed a large amount of ROMs to store the application program, be it Low Energy Bluetooth, BT audio, etc.,” said Frédéric Masson, Business Unit Manager at Dolphin Integration. “The superior density of our sROMet, which is known for enabling up to 35% area savings, partakes in ensuring the best competitive advantage in such cost-sensitive applications!”

To enable the cost-effective design of energy-efficient SoCs, Dolphin Integration is expanding its portfolio of foundation IPs at TSMC 40 nm to complement their existing offering of Power Fabric IPs. Complementary to this ROM compiler, a new generation of dense and low-power SRAM memory compilers (Single-port RAM TELESTO and Dual-port RAM ERA) is under completion as well as a standard-cell library (SESAME BiV) dedicated to always-on power domains.

About Dolphin Integration

Dolphin Integration is a pioneer in “enabling low-power Systems-on-Chip” for worldwide customers including all the major actors of the semiconductor industry – with a unique offering of high-density Foundation, Feature and SoC Fabric of Silicon IP components best suited for low power-consumption.

Over 30 years of experience in the integration of silicon IP components with complementary EDA solutions for a power-integrity driven approach to design, providing ASIC/SoC design and fabrication, have made Dolphin Integration a true one-stop shop for all customer needs.

It is not just one more supplier of Technology, but also the provider of the Dolphin Integration know-how!

If you liked reading our announcement please write to us at contact@dolphin.fr or visit us www.dolphin-integration.com

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