Synopsys to Boost Integration of PrimeTime Into IBM's Blue-Logic Design Flow

MOUNTAIN VIEW, Calif.----Sept. 29, 2000-- Synopsys, Inc. (Nasdaq:SNPS) today announced a unified timing verification flow between Synopsys' PrimeTime® and IBM's (NYSE:IBM) Blue Logic design methodology. PrimeTime support is available immediately for IBM's Cu-11, SA27 and SA27E process technologies. The seamless integration of Synopsys' industry-leading static timing analysis tool, PrimeTime, with IBM's advanced ASIC technologies gives mutual customers a consistent and proven static timing methodology for system-on-chip (SoC) design.

``Our customers need advanced design tools to meet their aggressive time to market needs,'' said Jim Dickerson, director of ASIC and EDA for IBM Microelectronics. ``IBM and Synopsys have been working together to provide a seamless flow between Synopsys' tools such as PrimeTime and Physical Compiler and our ASIC design environment. Continuing to collaborate with leaders like Synopsys to match their design tools to our environment makes it easier for our mutual customers to use IBM's libraries and technology.''

As part of an ongoing effort to build a unified timing verification flow between Synopsys tools and IBM Blue Logic, the companies have achieved excellent timing correlation between Synopsys' PrimeTime and IBM's Einstimer. Furthermore, the companies have cooperated on a timing constraints flow and the development of advanced analysis features such as on-chip variation and clock reconvergence pessimism removal.

``The integration of PrimeTime into the Blue Logic design flow provides our customers with proven static timing analysis and access to IBM's advanced silicon technology,'' said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Group. ``With the introduction of new silicon technologies, we look forward to expanding our partnership on static timing analysis to better address the future needs of our mutual customers.''

About Synopsys PrimeTime

PrimeTime is a full-chip, gate-level static timing analysis tool targeted for complex multimillion-gate designs. PrimeTime's integration into logical and physical design flows enables quick debugging of complex timing problems and speeds timing closure. PrimeTime is the industry-leading sign-off tool at semiconductor companies worldwide -- including Fujitsu, Hitachi, LSI Logic, NEC, STMicroelectronics, Texas Instruments and TAEC.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Contact:

     Synopsys, Inc.       Craig Cochran, 650/584-4230       craig@synopsys.com          or       KVO Public Relations       Leanne Frank, 503/221-7403       leanne_frank@kvo.com