Real Intent Introduces Conquest(TM) and Ascent(TM), Leading the New EnVision(TM) High-Performance Formal Verification Family

Conquest Leverages the "Assertion Density Paradox" for Breakthrough Results

SUNNYVALE, CA -- July 03, 2006 -- Real Intent, Inc., the leading supplier of formal verification software for electronic design, announced today that it is introducing the EnVision formal verification product family. New products Conquest and Ascent join existing products, Clock Intent Verification™ and PureTime™, to complete the family. EnVision is made up of Real Intent's leading formal verification solutions that are applicable from design specification, to design sign-off.

"Our customers continually state that high performance solutions to their verification problem are of extremely high value," said Prakash Narain, President and CEO, Real Intent. "Improving design quality, while minimizing engineering effort, is a goal we share with our customers. EnVision is our next major step towards achieving this goal."

About Conquest

Designed with the most challenging Assertion-Based Verification (ABV) needs in mind, Conquest moves beyond block-level verification to cluster-level verification. The combination of the industry's most powerful formal Convergence Engine™ with a new assertion visualization capability allows for more capacity and interactivity. Conquest also includes patented automatic proof construction as well as a guided iterative process. Together, these capabilities offer higher productivity than alternative solutions.

Conquest makes use of standard ABV languages and with its formal techniques is not dependent on vector quality for detecting design defects. With Conquest, users can verify their design using Property Specification Language (PSL) assertions, SystemVerilog Assertions (SVA), or Open Verification Library (OVL) checkers.

Conquest and the Assertion Density Paradox

With most ABV solutions, if one assertion is hard to prove, then many assertions are even harder. However, with Real Intent's patented technology, the opposite can be true --having many assertions can be easier to prove. To learn more about this paradox, visit us at Booth 706 at the Design Automations Conference (DAC), in San Francisco July 24-27.

About Ascent

Ascent is a significant step forward in automatic formal verification. Its redesigned architecture is focused on automatic checks that are derived from the Register Transfer Level (RTL) design. It supports PSL and SVA constraints and includes the Ascent SimPortal, which links to dynamic simulation. Ascent with the Convergence Engine also delivers higher performance, which results in faster proofs.

Ascent automatic verification is used for logic verification, to find bugs in RTL code even before simulation is possible. It is used as a signoff step before RTL is checked in to the design process. Ascent finds a comprehensive list of sequential design errors, including array bounds violations, full and parallel case pragma violations, Finite State Machine (FSM) deadlocks, and dead code. These errors are detected automatically without testbenches or running simulation.

About Clock Intent Verification & PureTime Products

Clock Intent Verification is the most powerful clock domain checking tool in the market. It acts as a final check to verify the functionality of the user's synchronization scheme and protects against errors with its debugging features.

PureTime is a timing-exception verifier that detects timing exception errors that create schedule delays, chip respins, or failing hardware. It proves the correctness of timing exceptions created by designers, or those delivered with Intellectual Property (IP), using exhaustive formal analysis. PureTime works throughout the entire design flow, with RTL or design netlists. PureTime verification reduces schedule risks for companies who use a manual review process for exceptions and increases accuracy.

Price & Availability

Ascent and Conquest ship in September. Clock Intent Verification and PureTime are available now. Prices for each tool range from $30k-$100k for a 1-year term license. Existing users with active maintenance contracts have an upgrade path.

About Real Intent

Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application-specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 35 major electronics design houses, including Sun Microsystems, ATI, Marvell Technology Group, nVidia, and NEC Electronics, use Real Intent software.

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: info@realintent.com.