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Novas Software Expands Debug Technology Platform for Complex System-On-Chip DesignAdvanced Platform Launches Next-Generation Behavior-Based Debug Capabilities; Knowledge-Based Architecture Evolved to Double System Performance and Capacity SAN JOSE, Calif.--(BUSINESS WIRE)--March 25, 2002-- Novas Software, Inc., the leader in debug systems for complex chip designs, today unveiled the second generation of its market-leading debug technology platform that introduces new behavior-based debug and knowledge management capabilities. It also delivers major architecture advances that double the performance and capacity of debug systems. Currently in use at 10 customer beta sites, these advancements are expected to both drive the next evolution in design exploration and debug for integrated circuit (IC) designs with 10 million+ gates and expand the benefits of faster, better debugging to the functional test programs associated with complex systems on chip (SoC). Debug helps design and verification engineers become familiar with how complex chip designs are supposed to function, and it locates and isolates design problems so their root causes can be analyzed, understood and corrected. This process is crucial to the successful completion of IC and SoC projects. However, according to Novas Software's president and CEO Scott Sandler, "Too much time is spent on debug, which raises product development costs and jeopardizes product schedules by draining valuable time from the most expert designers." Sandler added: "We are at a pivotal point in the evolution of design and verification. Sophisticated debug methods are no longer a luxury because the price tag for missing schedules is too high. It's critical that we take debug to a new level that not only maps to the most advanced design and verification approaches, but also intelligently applies knowledge to address bigger design issues and offer greater efficiencies. Our goal is really to reduce the overall time spent in debug, so resources can be applied to more creative tasks in the design process." Recent statistics on SoC design costs published by the International Technology Roadmap for Semiconductors (ITRS) project that one million dollars is added to the design budget for every month a project schedule slips.(1) Understanding Design Behavior Today's debugging tools rely on structural information alone, including the Debussy® knowledge-based debug system - Novas' current-generation product that is recognized as the debug market leader. When organized correctly, rapid access to this structural information is highly valuable for accelerating debug. The Company revealed today that new, patented technologies developed by Novas move debug from structural to behavioral abstractions. These use synthesis technology, as well as formal and semi-formal methods, to further improve the productivity of design and verification engineers facing the toughest debug challenges. By applying formal technologies to the tasks of design exploration and debugging, Novas believes it can minimize the risks associated with using unfamiliar design elements and significantly shorten debug cycles, ensuring that design teams meet schedules and avoid higher project costs. Specifically, new data models and exploration tools have been built on top of Novas' proven design knowledge architecture in order to help engineers better understand the dynamic behavior of their designs over time. The more unfamiliar the design, the greater the difficulty and the more time required to reach adequate understanding. To overcome this obstacle, Novas uses rigorous mathematical analysis of designs to automatically infer behavior. This technique was first applied in synthesis tools in the 1980's and is being applied today to functional verification in formal equivalence checking applications and some property-based verification tools. Key elements of Novas' new behavior-based debug technologies include:
New visual representations of the design that show the behavior of the design unrolled over time in terms of data/control flow and statement flow. Dynamic exploration tools that allow engineers to play "what-if" with their designs by changing simulation values and even register transfer level (RTL) statements to evaluate the consequences of these changes and understand the effect of alternatives before committing them to the source code and re-simulating. Building the tests that discover whether there are functional errors in a chip design has become at least as difficult as designing the chip itself. However, the tools for debugging design descriptions and test descriptions have evolved separately. Novas is expanding its system architecture to address the need for integrated design and testbench exploration and debugging. Key elements include: system-level enhancements and open application programming interfaces to the Novas KDB data model, new exploration and debugging products that transparently traverse designs and testbenches, and interoperability with third-party testbench automation tools. Novas' second-generation debug platform also captures critical design knowledge that typically remains with the engineers who create it. By storing this information and making it available throughout the development process, design teams can more productively reuse designs across time and distance. Key elements include: new automatic extraction and KDB storage capabilities, customizable viewing tools, and tight integration with design exploration and debugging tools. Dr. Paul Huang, Novas Software founder, chairman of the board of directors, and 2000 EDAC Kaufman award winner said: "As a technologist, I applaud the fundamental breakthrough technology of the Novas debug platform because it delivers performance, capacity and capabilities as fast as IC complexity grows. The Novas team led debug into the 90s' with a simulator-independent approach, and I'm confident in their ability to take debug into the next generation." Availability Beginning in the second quarter of 2002, Novas will release new software products that leverage the advanced capabilities and methodologies of its new debug technology platform. An enhanced performance version of the Novas Debussy knowledge-based debug system is also scheduled for release in the second quarter. About Novas Novas is the pioneer of advanced debug systems deployed by hundreds of companies worldwide to reduce functional verification costs for complex chip designs. Novas' leading-edge technology platform applies automation and design knowledge throughout the entire debug process to improve the efficiency of system-on-chip designers. Users report that the Company's initial offering, the Debussy® knowledge-based debug system, cuts in half the time it takes to locate, isolate and understand the causes of unexpected design behavior. Novas has over 7,000 systems in use today. For more information visit http://www.novas.com or send email to info@novas.com. Novas is located at: 2025 Gateway Place, Suite 480, San Jose, Calif. 95110. Phone: 408-467-7888. Fax: 408-467-7889, 1-888-NOVAS-38. Novas Software and Debussy are registered trademarks and Knowledge Database is a trademark of Novas Software, Inc. All other trademarks or registered trademarks are the property of their respective owners. (1)Note to Editors: The International Technology Roadmap for Semiconductors (ITRS) is an assessment of the semiconductor technology requirements. It is sponsored by the Semiconductor Industry Association (SIA), the European Electronic Component Association (EECA), the Japan Electronics & Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA . International SEMATECH is the global communication center for this activity. The ITRS web site is http://public.itrs.net/. Contact: Public Relations for Novas Wired Island, Ltd. Laurie Stanley, 510/656-0999 laurie@wiredislandpr.com or Novas Software, Inc., San Jose Lorie Bowlby, 408/467-7871 lorie@novas.com |
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