Imperas Donates Latest RV32/64K Crypto (scalar) Architectural Validation Test Suites to the RISC-V Verification Ecosystem

Imperas developed test suites released as open source under the Apache 2.0 license.

Oxford, UK – March 1st, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the release of the latest update to the RISC-V architectural validation test suites for the RV32/64K Crypto (scalar) extension. Developed in conjunction with the guidelines of the RISC-V International Architecture Tests SIG, Imperas has achieved an almost 100% functional coverage of the instructions based on the RISC-V Cryptographic Extensions task group’s functional coverage plan. The released tests support the RISC-V ISA Crypto specification proposed as the “K” extension, current draft spec 0.8.1, and will be updated as the spec is publicly reviewed and ratified.

Imperas has uploaded the new test suite to the official RISC-V International GitHub repository, available at https://github.com/riscv/riscv-arch-test, and the riscv-crypto repository is on GitHub at https://github.com/riscv/riscv-crypto.

In addition, Imperas has also updated the free RISC-V Open Virtual Platform Simulator, known as riscvOVPsimPlus™, as a reference Instruction Set Simulator (ISS) for users and developers of RISC V processor cores, with the new Crypto extensions, which is available on OVPworld.

“The new scalar cryptography extension for RISC-V is designed to be lightweight and to be suitable for 32- and 64-bit base architectures, from embedded, IoT class cores to large, application class cores,” said Richard Newell, Associate Technical Fellow at Microchip and Chair of the RISC-V International Cryptographic Extensions Task Group. “The working group coordinates the member driven contributions and we welcome the Imperas Crypto tests to support the early implementors and adopters.”

"The RISC-V open standard ISA offers a compatibility framework, yet has built-in flexibility across the specification envelope,” said Allen Baum of Esperanto Technologies, Inc., and Chair of the RISC-V International Architecture Test SIG. “The Imperas contribution of new Crypto extension tests is a welcome addition to the trusted test suite portfolio, supporting implementers with verification of their hardware."

“RISC-V International’s mission is to support the adoption of RISC-V through industry-wide partnerships and collaboration,” said Mark Himelstein, CTO of RISC-V International. “The continued contributions, including the Imperas Open Source Architecture tests, are helping to ensure an ecosystem of compatibility that all members and users can build on.”

“As the lead implementors complete the verification phase of the Crypto extensions, a final test case is needed for architectural validation,” said Simon Davidmann, CEO at Imperas Software Ltd. “Imperas developed these test suites for our commercial users, and we are now pleased to offer these as open source to support the growing RISC-V Verification Ecosystem.”

The free riscvOVPsimPlus package including the test suites and functional coverage analysis are now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus. The riscvOVPsimPlus solution is an entry ramp for development and verification and includes a proprietary freeware license from Imperas, which covers free commercial use as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license.

Availability:
The RV32/64K Crypto (scalar) Architectural Validation Test Suites are available now on GitHub at https://github.com/riscv/riscv-arch-test.

The free riscvOVPsimPlus package including many test suites and functional coverage analysis
is available on OVPWorld at https://www.ovpworld.org/riscvOVPsimPlus.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website at www.OVPworld.org.