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Lexra Debuts Lx4380: The Fastest Synthesizable 32-Bit Risc Core
Lexra Debuts Lx4380: The Fastest Synthesizable 32-Bit Risc Core
Lexra's new product targets living room consumer electronics and communications networking applications, where designers are integrating their packaged RISC processors into SOC designs. Previously, SOC designers searched for synthesizable RISC CPUs able to achieve performance comparable to packaged CPUs. Lexra's LX4380 is the first 32-bit RISC CPU core to effectively address this need. "We are excited to continue our performance lead in the 32-bit RISC core market," said Charlie Cheng, president and CEO of Lexra. "The LX4380 is a full 100 MHz and 100 MIPS better than any other 32-bit MIPS processor on the market. In markets where high performance has meant high selling price, and where SOC designs have not met the performance goal, the LX4380 is what our customers have demanded." The emerging requirement for high-performance in an SOC design has created the market opportunity for the LX4380. As software has become the critical element for communications and consumer electronics chips to add value, and reduce time-to-market, the need for processor's performance has escalated. Products such as DSL chips with multi-protocol capabilities, and interactive digital TV chips with web browsing and delay-playback, both require tremendous processing power. On the other hand, traditional EDA tools and time-to-market constraints have made it impossible for typical SOC design teams to extract the level of performance needed from a typical synthesizable processor. For example, Lexra's LX4189, the fastest synthesizable 32-bit processor currently shipping in the MIPS world, is only capable of 200 MHz clock speeds (in 0.18 micron technology). LX4380 Overview The LX4380's performance lead comes from three architectural innovations: a seven-stage pipeline, a new design partitioning that confines critical paths to smaller blocks of logic and a new capability called background move that eliminates the time a CPU loses waiting for data transfers to complete. The LX4380 employs a seven-stage pipeline while most 32-bit MIPS ISA based processors use a five-stage pipeline architecture. The performance of the five-stage design is quite sensitive to cache memory speed, something most fabless companies cannot control. Lexra's seven-stage architecture allocates one extra stage for instruction memory and one extra stage for data memory, permitting design teams to use off-the-shelf memory from Artisan Component and Virage Logic. For example, even at the maximum speed of 420 MHz, the LX4380 allows up to 32 Kbytes of instruction cache and 32 Kbytes of data cache. Furthermore, with the seven-stage pipeline the LX4380 also boasts a two-set, write-back cache, typically found on 64-bit IP but rare on 32-bit IP cores. A combination of the extra pipeline stage and byte addressable memories from memory suppliers Virage and Artisan, make the write-back cache possible. The advantage to this type cache is improved system bus utilization. On average assuming a cache line has four words, and on average two words per write are in cache then bus utilization improves by more than two-fold. Another innovation, a new design partition of the modules comprising the LX4380, eliminates critical paths between major blocks in the CPU clock domain. "Before, when one of our LX4189 customers did back-end layout, he or she invariably found critical paths across multiple Verilog modules," said Pat Hays, Lexra's CTO. "Once the critical path crosses a Verilog boundary, it is hard to optimize timing on the net. The new partitioning, which confines critical paths to a single Verilog module greatly eases timing optimization of critical nets. The result is hard core performance from a soft core ASIC design methodology." The CPU core is divided into three clock domains: CPU, system, and EJTAG (see figure). In previous generations, most of these blocks ran at the same speed as the CPU. Thus, the CPU could run no faster than its slowest block. By re-partitioning, only the CPU needs to run at the 420 MHz speed, greatly simplifying the VLSI implementation task. The system logic can run either at one-half or full CPU speed, depending on the application requirement. Other clock divide ratios will be supplied in the future to support planned moves to even higher CPU speeds. The EJTAG block is clocked asynchronously at lower speed. The LX4380 supplies the necessary EJTAG synchronization logic. The introduction of background move is another Lexra innovation. Embedded applications are data intensive. About one to three percent of embedded application software comprises instructions for loading and storing data to and from external sources. During this time, the CPU sits idle waiting for the blocked move to complete. If two percent of embedded software is I/O instructions, the CPU sits idle 10 percent of the time. The LX4380's solution is a background move, a DMA-like transfer to and from local CPU memory. The transfer can be from any length up to the full size of data memory, and the CPU will continue to execute without stalls while waiting for the data transfer to complete. Once the data is in local memory, the LX4380 has a 64-bit twin register load operation to rapidly transfer data between data memory and the general register file. Even/odd pairs of 32-bit registers can be loaded in one cycle. In addition to these innovations, the LX4380 also supports an optional multiply-accumulate engine that completes one MAC instruction every cycle, for performance in signal processing applications such as software modems. The LX4380 also has a Linux-optimized memory management unit (MMU), which is optional to all six- and seven-stage Lexra RISC/DSP cores. It uses a 4-Kbyte-page size, 16-, 32- or 64-entry joint translation lookaside buffer (TLB). Lexra's seven-stage pipeline permits the caches to be physically, rather than virtually indexed to improve performance. Lexra's partner, Amirix Systems Inc. of Halifax, Nova Scotia, Canada wrote the Linux software for the MMU and in the spirit of Linux, the code is in the public domain. Software support is available directly from Amirix. Specification, Pricing, and Availability Lexra's LX4380 is optimized for 0.13 micron process technologies. It occupies 1 mm2 in area, and delivers 420 MHz under typical semiconductor process conditions and 360 MHz under worst-case process, worst-case commercial conditions for a typical 0.13-micron ASIC process at TSMC and UMC. Power dissipation for a basic configuration of the core is 47 mW worst case. The LX4380 will begin first customer shipment in Q3, 2001. General availability will occur in Q4, 2001. Single project license fee for RTL is $568,000. About Lexra Lexra, Inc. is a leading microprocessor developer specializing in 32-bit RISC and DSP cores for the embedded market. In less than four years, Lexra has established itself as an innovator in embedded microprocessor technology and intellectual property (IP) licensing business model, with proven track record for customer success. During this short period, Lexra has delivered seven processors to 30 licensees in six different countries. Among the customers are major network communication companies as well as top ten semiconductor companies. Lexra is headquartered in San Jose, CA. Further company information can be found at http://www.lexra.com. *MIPS, MIPS I, MIPS16, R3000, and other MIPS common law marks are trademarks and/or registered trademarks of MIPS Technologies, Inc. Lexra, Inc. is not associated with MIPS Technologies, Inc. in any way. Unaligned loads & stores are not supported in hardware or software. For Immediate Release Lexra Contact: Press Contact: |
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