Avertec and Dolphin Integration announce partnership in Design Check Innovation

San Diego, California - June 7, 2004 - Dolphin Integration SA and Avertec Inc. today announced that they have entered into a partnership to deliver innovative solutions by linking different levels of design abstraction as specified by the Alliance for the Virtual Socket Interface.

"The new solution will enable designers to correlate functional, electrical and physical views of a design, and thus perform new kinds of verification, such as exhaustive functional validation or memory scrambling analysis", said Gilles Augustins, Applications Manager for Avertec.

The flow integrates Dolphin Integration's layout Analyzer and Socket-builder SoC GDS together with Avertec's functional Abstractor YAGLE. The first release is focused on the most urgent need for Memory verification. The solution being patented by Dolphin Integration shall enable extensions to all types of circuitry, up to mixed signal, for which it provides the ultimate Virtual Test, Diagnostic and Instrumentation capability.

SoC GDS gives the ability to view the propagation of logic states as switching events on the circuit layout, much like a Virtual Electronic Scanning Microscope displaying active signals. It enables the location of the interconnections which carry logic events through the hierarchy of the layouts by linking them with logic simulation results. The user can specify which interconnections are displayed, as well as the time interval to observe, either to analyze potential glitches during design partaking in better Design for Yield (DfY), or to prepare silicon inspection preparing better Design for Manufacturing (DfM).

YAGLE generates a behavioural description of the design from the transistor netlist, and thus makes the link between the electrical and functional views. Furthermore, the behavioural description is automatically annotated with precise timings, allowing already any kind of memory design to be handled.

The development of the solution was partially supported by the MEDEA+ Project T-101 TECHNODAT. "Dolphin Integration and Avertec developed a strong cooperation on this project. We have responded to requests from customers and partners to integrate our technology, and to offer comprehensive support and distribution", said Loïc Decloedt, Project Manager for Dolphin Integration.

About Dolphin Integration
Dolphin Integration was created in 1985 at a time when a strong growth was expected from Mixed signal ASIC Design Services. It now has a rich history as a Chipless Microelectronics Development Center experienced in design of library cells, of mixed analog/digital and pure logic IC's, and Fabless supplier of custom IC's. It also leads its own R&D strategy which is translated in a portfolio of key patents and key algorithms to be embedded either in software or hardware.

After ten years of maturation in a California dominated high-tech market, and of strengthening in Chipless Mixed signal IC design skills and tools, this Enterprise has undergone in July 1994, a drastic cultural reassessment and has put itself on a new course toward aggressive growth with an innovative product strategy on dual markets:
Intellectual Property in Microelectronics, so-called Silicon IP, commercialized as FLIP™ which stands for FabLess IP, strong in Analog Codecs and PPL's, embedded Memories, and 80251 Logic; and

Missing Electronic Design Automation Links, commercialized under the acronym MEDAL™. It encompasses the unique mixed signal and multi-level Simulator SMASH and SoC GDS mainly focused on Time-to-Fab of systems-on-Chips.
For more information visit http://www.dolphin.fr

About Avertec
Avertec is a privately held company created in 1998. Its mission is to provide solutions for the back-end verification of complex designs. The company develops and commercializes solutions for Timing, Crosstalk, Power and IR Drop analysis.

Avertec has an innovative Transistor level methodology based on proven HiTAS and YAGLE platforms. Realistic full chip validation is provided by combining Static and Dynamic analysis of an abstracted Timing and/or Functional model that is close to the physical implementation.

The company is headquartered in the Paris area, France, has a sales office in San Jose, California and represented by distributors in Japan and in Asia. Avertec is a member of the EDA Consortium.
Further information at http://www.avertec.com