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• NVMe Updates Expand Discoverability, Security (Monday, October 7, 2024)
• EXTOLL collaborates with Frontgrade Technologies for High-Speed SerDes IP (Tuesday, October 1, 2024)
• Silicon Creations Awarded TSMC's 2024 Open Innovation Platform Partner of the Year for Mixed Signal IP (Wednesday, September 25, 2024)
• MIPI Alliance Releases A-PHY v2.0, Doubling Maximum Data Rate of Automotive SerDes Interface To Enable Emerging Vehicle Architectures (Wednesday, September 25, 2024)
• M31 Launches ONFi5.1 I/O IP on TSMC 5nm Process (Wednesday, September 25, 2024)
• EXTOLL collaborates with BAE Systems as a Key Partner for High-Speed SerDes IP (Wednesday, September 25, 2024)
• eMemory Won TSMC OIP Partner of the Year Award for the Outstanding Development of its NVM IP on Advanced Nodes (Wednesday, September 25, 2024)
• Certus Semiconductor releases I/O library in TowerJazz's 65nm process (Tuesday, September 24, 2024)
• GUC Announces Adoption of HBM3E IP by CSP Data Center (Monday, September 23, 2024)
• Alphawave Semi and InnoLight Extend PCIe over Optics Collaboration with Demonstration of 128Gbps Gen 7.0 over Low Latency Linear Pluggable Optics at ECOC 2024 (Monday, September 23, 2024)
• XtremeSilica Successfully Ships First SDRAM Controller for Tapeout GF40nm (Sunday, September 22, 2024)
• Omni Design Technologies extends partnership with EnSilica and expands Swift™ Data Converter IP portfolio (Sunday, September 22, 2024)
• JEDEC® Adds to Suite of Standards Supporting Compute Express Link® (CXL®) Memory Technology with Publication of Two New Documents (Sunday, September 22, 2024)
• Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the TSMC 2024 Open Innovation Platform Ecosystem Forum (Sunday, September 22, 2024)
• Cadence Tensilica HiFi 5 DSPs Used in NXP's Next-Gen Audio DSP Family (Tuesday, September 17, 2024)
• CAST Ships I2C/SPI Controller IP Core for Easier Serial Communication (Wednesday, September 4, 2024)
• Advanced USB 3.0 IP in 22nm boasting a very low power ULP and ULL Technology Licensed to Over 10 Global Customers (Sunday, September 1, 2024)
• Arasan Announces immediate availability of its I3C Host / Device Dual Role Controller IP (Thursday, August 29, 2024)
• JEDEC Releases New Standard for LPDDR5/5X Serial Presence Detect (SPD) Contents (Thursday, August 22, 2024)
• Axiomise Showcases Value of Formal Verification at DVCon Japan and DVCon India (Tuesday, August 20, 2024)
• ADC IP - 14-Bit, 4.32 GSps Silicon-Proven: Now Available for Whitebox Licensing with No Royalty (Tuesday, August 20, 2024)
• Everspin Announces a $9.25M Contract to Provide MRAM Technology for Strategic Radiation Hardened eMRAM Macro (Monday, August 19, 2024)
• The Uberization of Engineering (Thursday, August 8, 2024)
• Imec demonstrates logic and DRAM structures using High NA EUV Lithography (Wednesday, August 7, 2024)
• NVM Express Releases NVM Express Specifications to Unify AI, Cloud, Client, and Enterprise Storage (Wednesday, August 7, 2024)
• Consult Red Announces Strategic Partnership with CAST, Inc. (Tuesday, August 6, 2024)
• NVM Express Releases NVM Express Specifications to Unify AI, Cloud, Client, and Enterprise Storage (Tuesday, August 6, 2024)
• Samsung Electronics Begins Mass Production of Industry's Thinnest LPDDR5X DRAM Packages for On-Device AI (Tuesday, August 6, 2024)
• ZeroPoint Technologies introduces LZ4 Compression and Decompression Hardware IP (Monday, August 5, 2024)
• Imec: Getting High-Precision Sensors to Market (Monday, August 5, 2024)
• T2M-IP Unveils MIPI D-PHY v2.5 Tx and DSI Tx Controller v1.2: Silicon-Proven, Low-Power, Cost-Effective IP Core Solutions for Advanced SoCs (Monday, August 5, 2024)
• DDR5 Gains Enhanced Security, Reliability, and Power Management Features (Friday, August 2, 2024)
• M31 cooperates with Tower Semiconductor to develop advanced SRAM and ROM solutions for its 65nm Power Management Platform (Thursday, August 1, 2024)
• Weebit Nano and DB HiTek tape-out ReRAM module in DB HiTek's 130nm BCD process (Wednesday, July 31, 2024)
• Weebit Nano moves closer to availability at DB HiTek; tapes out first chip (Wednesday, July 31, 2024)
• Rambus Expands Industry-Leading Memory Interface Chip Offering to High-Performance PCs with DDR5 Client Clock Driver (Tuesday, July 30, 2024)
• Weebit Nano to present test results of ReRAM performance on GlobalFoundries 22FDX® wafers at FMS 2024 (Monday, July 29, 2024)
• Raaam signs lead licensee for SRAM replacement technology (Monday, July 29, 2024)
• Silicon-Proven 14-Bit 4.32 GSps Wide Band ADC IP Core with Time-Interleaved Pipeline Architecture Now Available for Whitebox Licensing with No Royalty Fees (Monday, July 29, 2024)
• DDR5 Gets More Security, Power Management Features (Friday, July 26, 2024)
• Agile Analog delivers customizable IP on GlobalFoundries' FinFet and FDX processes (Thursday, July 25, 2024)
• MIPI C-D Combo PHY and DSI Controller IP Cores, Silicon Proven, Immediate licensing at a Competitive Price for Your Next Project (Monday, July 22, 2024)
• JEDEC Unveils Plans for DDR5 MRDIMM and LPDDR6 CAMM Standards to Propel High-Performance Computing and AI (Monday, July 22, 2024)
• Samsung Completes Validation of Industry's Fastest LPDDR5X for Use with MediaTek's Flagship Mobile Platform (Tuesday, July 16, 2024)
• Qualitas Semiconductor Announces First Domestic Development of PCIe 6.0 PHY IP (Tuesday, July 16, 2024)
• AI-driven SRAM demand needs integrated repair and security (Monday, July 15, 2024)
• Samsung to mass-produce HBM4 on 4 nm foundry process (Monday, July 15, 2024)
• OPENEDGES Successfully Validated Its 7nm HBM3 Testchip (Sunday, July 14, 2024)
• L&T Semiconductor Technologies Partners with CP Plus to develop Semiconductor Chips for CCTV Camera Solutions (Sunday, July 14, 2024)
• Advanced MIPI DSI Tx & Rx Controller IP Cores: Low-Power, Cost-Effective Solutions for Modern Display SoCs (Sunday, July 14, 2024)