SILABTECH JESD204B SERDES PHY IP running up to 12.5 Gbps in a single lane.
The SERDES comply with the JEDEC standard.
The IP can be designed with Single/Multi lane configurations- Reach the 100 Gbps interconnect with our 8 Lanes design.
TSMC 28HPM - Silicon Proven
SMIC 40LL- Silicon Proven
GF 28SLP- Silicon Proven (up to 6 Gbps per lane)
GF 40LP- GDS Ready (up to 6 Gbps per lane)
TSMC 55LP- Tx 10Gbps / Rx 8Gbps
Data Rate programmable 0.3-12.5 Gbps
JESD204B SERDES is supported with SILABTECH own Controller.
SILABTECH Controller is available either as bundle or as a Stand Alone IP (soft macro).
- Transmit Driver with programmable output swing 100 mV 1200 mVp2p
- Pre/Post cursor Transmit equalization range 0 ¡V 12db with 20mV programmability step
- Adaptive Receiver equalization (CTLE + DFE) for channel with insertion loss up to 30db at 6GHz
- Embedded low jitter phase-locked-loop (PLL) with 0.8ps rms RJ (filtered with single pole 4MHz HPF)
- Spread spectrum clock generation with up to 5000ppm down-spread
- Beacon, Out-of-band (OOB) Signaling, Low-Frequency-Periodic-Signaling (LFPS), Auto-negotiation (AN) Signaling supported
- Standard Interface with SOC
- Standard specific PCS layer provided with the SERDES enables standard interface with the SOC
- DFT & Test
- Rich in DFT features (AC-JTAG, Eye-scan, Loop-back, RX Sensitivity BIST, TX level BIST, PLL BIST)
- Stuck-at & TFT scan for digital
- Boundary scan (Extest) for integration with SOC scan compressor
- Tests can be done on low cost digital tester
- Low active and stand-by power (disclosed under NDA)
- All power-saving modes implemented for aggressive power saving (disclosed under NDA)
- Low Area (disclosed under NDA)
- JEDEC JESD204B is well adopted standard for high speed connection between high end ADC/DAC and host process/FPGA.
- Flexible number of Tx & Rx Lanes per your application needs.
- Lowest Power and Area in the industry.
- Customization Services for specific applications and processes.
- Specification and integration document.
- Physical models : LEF, GDSII
- Spice models for LVS.
- CLP models for low power aware designs.
- Timing models (.libs)
- Simulation models (behavioral and board simulation)
- DFT models and test vectors
- Reference Board with FPGA
- Characterization and compliance reports.
- JESD204B is used for Chip-To-Chip high speed connectivity.
- Chip-To-Chip, either directly or through Backplane, for high speed interconnect ADC/DAC such as AD9680 14bit 1GSPS ADC.
- Connectivity between Host Processor and peripheral components and wireless modules.
Block Diagram of the 0.3-12.5 Gbps JESD204B SERDES PHY & Controller