SILABTECH Multi-standard programmable SERDES IP was designed and validated on TSMC 28 HPM.
The SERDES can be used as a Single or a Multi lane configuration- Reach the 100 Gb/Sec interconnect with our 8 Lanes design.
Support the following standards:
PCIe Gen 1-2-3
SATA Gen 1-2-3
USB SuperSpeed 3.0 & 3.1 with Type C Support
HSSTP (High Speed Serial Taping Port)- Debug Port
Display Port , eDP
HMC- Hybrid Memory Cube Interface
CPRI- Common Public Radio Interface
EPON/GPON/XGPON with unique Burst CDR functionality.
TSMC 28HPM/HPC - Silicon Proven
TSMC 55LP- Silicon Proven
SMIC 40LL- Silicon Proven
GF 28SLP. 40LP- 6.25Gbps versions silicon proven
For JESD204B SERDES and Controller- please check P/N SB-JESD204B
Data Rate programmable 0.3-12.5 Gbps
SERDES IP Core can be migrated to other Tech node and foundries- Contact us for more details.
- Transmit Driver with programmable output swing 100 mV 1200 mVp2p
- Pre/Post cursor Transmit equalization range 0 ¡V 12db with 20mV programmability step
- Adaptive Receiver equalization (CTLE + DFE) for channel with insertion loss up to 30db at 6GHz
- Embedded low jitter phase-locked-loop (PLL) with 0.8ps rms RJ (filtered with single pole 4MHz HPF)
- Spread spectrum clock generation with up to 5000ppm down-spread
- Beacon, Out-of-band (OOB) Signaling, Low-Frequency-Periodic-Signaling (LFPS), Auto-negotiation (AN) Signaling supported
- Standard Interface with SOC
- Standard specific PCS layer provided with the SERDES enables standard interface with the SOC
- DFT & Test
- Rich in DFT features (AC-JTAG, Eye-scan, Loop-back, RX Sensitivity BIST, TX level BIST, PLL BIST)
- Stuck-at & TFT scan for digital
- Boundary scan (Extest) for integration with SOC scan compressor
- Tests can be done on low cost digital tester
- Low active and stand-by power (disclosed under NDA)
- All power-saving modes implemented for aggressive power saving (disclosed under NDA)
- Low Area (disclosed under NDA)
- Multi-Standard compliant SERDES PHY
- Wide range of data speed supported on the same IP- continues range.
- Flexible number of Tx & Rx Lanes per your application needs
- Lowest Power and Area in the industry.
- Customization Services for specific applications, protocols and processes- Can be migrated to any CMOS process up to 130nm- call us for a free feasibility study.
- Specification and integration document.
- Physical models : LEF, GDSII
- Spice models for LVS.
- CLP models for low power aware designs.
- Timing models (.libs)
- Simulation models (behavioral and board simulation)
- DFT models and test vectors
- Reference Board with FPGA
- Characterization and compliance reports.
- USB / PCI / SATA are used in Consumer Electronics; Industrial, Measurement and Computing systems.
- XUAI, 10GBase-KR and CEI-OIF are used for Chip-To-Chip, either directly or through Backplane, for high speed interconnect.
- HMC is used for advance Memory chips where few types of memory cells are integrated.
- CPRI is used for advance Radio equipment (LTE; 4G; 5G).
- XFI is used to interconnect with Optical Modules (SFP, SFP+)
Block Diagram of the 0.3-12.5 Gbps Multi-Standard SERDES PHY (PCIe, SATA, USB 3.0/3.1, 10GBase-KR, PON, XAUI)