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Audio codec with capacitor-less 104 dB dynamic range ADC and 100 dB DAC
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10-bit, 12-bit, 14-bit, Low Speed SAR ADC in GlobalFoundries (40nm, 22nm, 12nm)
With more than 17 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs).
Synopsys’ strong application expertise in areas such as mobile communications, cellular IoT, and wireless connectivity (i.e., LTE/LTE-A, NBIOT/CAT-M, WiFi.11ac/ax), wireline communications (i.e., PLC, G.hn, MoCA), IF demodulation, video, imaging and multimedia results in high-quality data converter IP that helps system-on-chip (SoC) designers meet their specific design requirements.
The DesignWare Data Converter IP offers very high performance, high speed, ultra-low power dissipation, and small area, and supports a wide range of foundry process technologies ranging from 180-nm to 12-nm. Synopsys’ high-quality DesignWare Data Converter IP solutions have been implemented in more than 300 SoCs, giving designers confidence that they can successfully integrate high-performance analog IP into their SoCs with less risk and improved time-to-results.
Synopsys’ strong application expertise in areas such as mobile communications, cellular IoT, and wireless connectivity (i.e., LTE/LTE-A, NBIOT/CAT-M, WiFi.11ac/ax), wireline communications (i.e., PLC, G.hn, MoCA), IF demodulation, video, imaging and multimedia results in high-quality data converter IP that helps system-on-chip (SoC) designers meet their specific design requirements.
The DesignWare Data Converter IP offers very high performance, high speed, ultra-low power dissipation, and small area, and supports a wide range of foundry process technologies ranging from 180-nm to 12-nm. Synopsys’ high-quality DesignWare Data Converter IP solutions have been implemented in more than 300 SoCs, giving designers confidence that they can successfully integrate high-performance analog IP into their SoCs with less risk and improved time-to-results.
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