The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY is small in area and provides a low-power, cost-effective solution that is designed to support PCI-SIG PCIe 3.1, 2.1, and 1.1 specifications and to meet the needs of applications with high-speed chip-to-chip, board-to-board, and backplane interfaces. In addition, its low power consumption cuts both active and standby power for mobile SoCs.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCIe standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The DesignWare PHY IP for PCIe 3.1 reduces both product development cycles and the need for costly field support by employing internal test features. The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity.
Synopsys offers a portfolio of silicon-proven IP for PCIe consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCIe, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
- Built-in self-test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
- Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing
- Industry's leading, complete PCI Express 3.1 IP solution: digital controllers, PHY and verification IP
- Supports advanced 28-nm and 14/16-nm FinFET technologies and flip-chip packaging
- Supports all the required features of the PCIe 3.1 (8.0 GT/s), 2.1 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications as well as the PIPE 3 and 4 (8-bit, 16-bit and 32-bit) specifications
- Supports a wide range of PCI Express lane aggregation up to 16-lanes and full bifurcation
- Includes robust backchannel initialization and advanced power management features including L1 sub-states in conjunction with power gating techniques
- Exceeds electrical specifications in areas of margin and receive sensitivity for a robust design
- Verilog models; Liberty timing views (.lib)
- LEF abstracts (.lef); CDL netlist (.cdl)
- GDSII; ATPG models
- IBIS-AMI models; SPICE models for Tx and Rx