The S3DA1M12BT65LP employs a current steering architecture. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture. The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit DAC features an excellent static performance that includes ±0.5LSB DNL and ±1LSB INL. Dynamic performance highlights considering a signal frequency with 50kHz and 1MS/s conversion rate include an SNR of 70dB and an SFDR of 78dBc. The S3DA1M12BT65LP is designed in a 65nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- 65nm TSMC LP Process, 6 Metals Used
- No Analog Options
- 3.3V and 1.2V Supplies
- Sampling Rate up to 1MS/s
- 1mA Output Full-scale range
- Only 4mW at 1MS/s
- DNL< 0.6LSB Typ.; INL< 1LSB Typ.
- SNR = 70dB, SFDR = 78dB for Fout = 50kHz
- Stand-By and Power-Down Modes
- Compact Die Area
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
- WiFi 802.11X, WiMAX 802.16x
- Direct Digital Synthesis
Block Diagram of the 12-Bit 1MS/s Current Steering DAC