The S3ADS20M12BT18 is a compact and low power 12-bit SAR ADC IP with a sampling rate up to 20MS/s.
This 12-bit ADC features an outstanding dynamic performance that includes 63.6dB SNR, 76dB SFDR and 10.2-bit ENOB. It also features an outstanding static performance with < ± 0.9 LSB DNL (no missing-codes) and < ± 1.5 LSB INL.
- TSMC 0.18um process
- 1.8V Core Domain Supply
- 12-bit SAR ADC
- Sampling Rate up to 20MS/s
- External Reference with Internal Buffer
- Single-Ended or Differential Inputs.
- Input Range in Single-Ended mode: 1.0Vpp
- Input Range in Differential mode: 1.0Vppdiff
- Gain Error < 3%
- Input Referred Offset < 1%
- Static Performance:
- DNL < ±0.9 LSB (no Missing-Codes)
- INL < ±1.5 LSB
- Dynamic Performance:
- 63.6dB SNR
- 63.2dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist incl. Ref. Buffer]
- Clock-Gated, Standby and Power-Down Modes
- Low Power Dissipation: 5mW
- Compact Die Area: 0.304mm2
- For application flexibility, this IP includes a Reference Buffer to drive the SAR ADC capacitive DAC.
- Considering a 20MS/s sampling rate, this ADC power dissipation is only 5mW, including the Reference Buffer. A calibration algorithm enhances the ADC performance.
- During calibration, analog inputs are kept in high impedance, therefore relaxing the requirements for the block driving the ADC.
- The S3ADS20M12BT18 can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Wireless Communications
- Wireline Communication Networks
- Home Network
Block Diagram of the 12-bit 20MS/s ADC IP Core