12-bit 320MS/s High-Speed SAR ADC

Features

• SMIC 40nm Low Leakage Process (LL)
• No Analog Options
• 1.1V Core & 2.5V I/O Supplies
• 12-bit ADC, High-Speed SAR-based Architecture
• Differential Input Signal Range: 1.0Vppdiff
• Sampling Rate: 320MS/s
• Internal Bandgap and Biasing System
• All Required Voltage References Included
• No External Accurate Reference Required
• No External Reference Decoupling Required
• Good Power-Supply Noise Rejection
• Outstanding Dynamic Performance
• 78.9dB SFDR at fin=10.7MHz
• -77.6dB THD at fin=10.7MHz
• 62.4dB SNR at fin=10.7MHz
• 62.3dB SNDR at fin=10.7MHz
• 10.0-bit ENOB at fin=10.7MHz
• [Noise integrated from DC to Nyquist]
• Stand-by and Power Down Modes
• Ultra Low Power Dissipation:

Benefits

• Robust Performance
• Low Power
• Low Area
• The S3ADS320M12BSM40LL does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (tlf)
• Behavioral Model (VHDL/Verilog)
• Integration Support

Applications

• Connected Consumer Devices
• LTE-A
• 802.11ac/ax
• DSL
• Imaging
• MIMO

Block Diagram of the 12-bit 320MS/s High-Speed SAR ADC

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