14-bit 1.2MS/s SAR ADC

Features

• TSMC 40nm ULP (Ultra Low-Power Process)
• 1.62V up to 3.63V I/O Supply
• 0.9V Core Supply
• 14-bit SAR ADC
• Re-configurable for 14 / 12 / 10 / 8 bit ADC Mode
• Sampling Rate up to 1.2MS/s
• Power Scales with Sampling Rate
• 16 MUX Input Channels:
• 2 Fully-Differential Input
• 14 Pseudo-Differential Unipolar Input
• Input Signal Range: 0 to VREF
• External Reference VREF:
• 1.5V or 2.0V
• Input Capacitance: 3.6pF
• Gain Error < 1%
• Input Referred Offset < 1%
• Static Performance:
• DNL < ± 0.9 LSB (no Missing-Codes)
• INL < ± 2.0 LSB
• Outstanding Dynamic Performance:
• 74.0dB SNDR
• 12.0-bit ENOB
• Conversion and Idle Modes
• Ide Mode:
• No Power Dissipation
• No Wake-Up Time
• Ultra Low Power Dissipation:

Benefits

• To allow for application flexibility whilst offering minimum area and power dissipation, the S3ADS1M14BT40ULP IP is an ADC core that does not include voltage generation and buffering. It can readily leverage from existing references, or if required a customized solution for a bandgap and/or a reference buffer can be included.
• The S3ADS1M14BT40ULP can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioral Model (Verilog)
• Integration Support

Applications

• Motion and Environmental Sensing
• Industrial Control
• Home Automation
• Consumer Electronics
• Auxiliary Control

Block Diagram of the 14-bit 1.2MS/s SAR ADC IP Core

• see the entire 14-bit 1.2MS/s SAR ADC datasheet
• get in contact with 14-bit 1.2MS/s SAR ADC Supplier