16G PHY, TSMC 16FFC x2, North/South (vertical) poly orientation

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 16G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications. The PHY is small in area and provides a low active power, standby power, cost-effective solution that supports multiple electrical standards, including PCI Express 4.0, SATA 6G, Ethernet 40/10GBASE-KR/KR4, 10GBASE-KX4/XAUI, 1000BASE-KX/SGMII and more, meeting the needs of applications with high-speed port side, chip-to-chip, board-to-board, and backplane interfaces.

The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation that is appealing to broad range of end markets from mobile to high-end networking. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional supply under drive. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and a broad range of digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and the need for costly field support.