16G PHY, TSMC 16FFC x2, North/South (vertical) poly orientation
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation that is appealing to broad range of end markets from mobile to high-end networking. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional supply under drive. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and a broad range of digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and the need for costly field support.
Features
- Operating from 1.23 to 16 Gbps 1 data-rate; PCI Express (PCIe) 4.0/3.1/2 .1/1.1, 1 with lane margining
- IEEE 802.3 10 to 40G backplane 1 (XAUI, KR & KR4), port side 1 1 to 100G (XFI, SFF-8431/SFI, 1 CR4 & CR10); SGMII and QSGMII (1.25 to 5G)
- SATA 6G/3G/1.5G; CEI-6G and CEI-11G up to 11.1 Gbps
- Serial Rapid IO (SRIO) up to 1 0.3125 Gbps; CPRI, OBSAI, JESD204B up to 1 2.5 Gbps
- Aggregation (x2 to x16 for PCIe) and 1 full-protocol bifurcation support; Auto-negotiation (AN) and optional 1 forward error correction (FEC)
- PCIe L1 substate power 1 management and SRIS; IEEE 802.3az Electrical Energy 1 Efficient (EEE)
- Continuous adaptation and 1 calibration with multi-tap adaptive 1 and configurable CTLE and DFE; Built-in self test (BIST) including 1 pseudo random bit stream (PRBS) 1 generation and checker
- Embedded BER tester and internal 1 eye monitor
- Supports -40C to 125C Tj
Deliverables
- Verilog models
- Liberty timing views (.lib)
- LEF abstracts (.lef); CDL netlist (.cdl)
- GDSII; ATPG models; IBIS-AMI models
- HSPICE models for Tx and Rx; Documentation
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16G PHY
- 16G Multi-protocol SerDes PHY
- Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
- 16G PHY, TSMC 16FFC x4, North/South (vertical) poly orientation
- 16G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
- 16G PHY, TSMC 28HPCP x1, North/South (vertical) poly orientation
- 28Gbps Multi-Standard SerDes PHY