Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process G/LV
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memory compiler IP
- Ultra High-Speed Cache Memory Compiler
- TSMC CLN12FFC Ternary Content Addressable Memory Compiler
- TSMC CLN5FF Ternary Content Addressable Memory Compiler with Column Redundancy
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- Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k