The Digital Blocks DB1820 Chroma Resampler IP Core down converts 4:4:4 YCbCr to 4:2:2 YCbCr in accordance with the ITU-R BT.601 standard requirements. The DB1820 accepts 4:4:4 YCbCr digital components and timing control signals and decimates by 2 the Chroma samples 4:2:2 YCbCr components. Control & Status, including the decimate filter coefficients, can be programmed into optional DB1820 registers via a bus interface, or set as non-register fixed parameters at synthesis for a smaller VLSI footprint.
- 4:4:4 YCbCr and 4:2:2 YCbCr input & output components each at 8- or 10-bits, unsigned data type. User selectable at 24- or 30-bit parallel or serial input / output
- Coefficients are 3-bit fractional data type
- Control signal enable for start-up and blanking period disabling
- After down conversion, each CbCr sample component can be truncated or rounded-up, and saturated or clamped for overflow or underflow, respectively
- Equalization of Y component and optional delay for display VSYNC, HSYNC, and DE signals
- User optional Slave Bus Interface for programming Control & Status Registers, which includes the down converters coefficients, or fixed parameters set at synthesis
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.