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Linear regulator with ultra low quiescent current for retention applications
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40G MP SerDes PHY (PCIe Gen1-5) 7nm
The AXLinkIO MP IP utilizes the silicon-proven AXLinkIO transceiver architecture.
The AXLinkIO MP IP from AnalogX is compatible to several protocols including PCI Express Gen1-5, JESD, OIF, CPRI, Ethernet, and others
The AXLinkIO MP IP from AnalogX is compatible to several protocols including PCI Express Gen1-5, JESD, OIF, CPRI, Ethernet, and others
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